Re: [Qemu-devel] [RFC PATCH 05/21] target-arm: add CPU Monitor mode

[Peter Crosthwaite]

On Wed, Dec 4, 2013 at 8:01 PM, Fedorov Sergey <address@hidden> wrote:
>
> On 12/03/2013 04:51 PM, Peter Maydell wrote:
>>
>> On 3 December 2013 12:20, Peter Crosthwaite
>> <address@hidden> wrote:
>>>
>>> On Tue, Dec 3, 2013 at 6:48 PM, Sergey Fedorov <address@hidden>
>>> wrote:
>>>>
>>>> From: Svetlana Fedoseeva <address@hidden>
>>>>
>>>> Define CPU monitor mode. Adjust core registers banking. Adjust CPU VM
>>>> state info. Provide CPU mode name for monitor mode.
>>>>
>>>> Signed-off-by: Svetlana Fedoseeva <address@hidden>
>>>> Signed-off-by: Sergey Fedorov <address@hidden>
>>>> ---
>>>>   target-arm/cpu.h       |    7 ++++---
>>>>   target-arm/helper.c    |    3 +++
>>>>   target-arm/machine.c   |   12 ++++++------
>>>>   target-arm/translate.c |    2 +-
>>>>   4 files changed, 14 insertions(+), 10 deletions(-)
>>>>
>>>> diff --git a/target-arm/cpu.h b/target-arm/cpu.h
>>>> index 0b93e39..94d8bd1 100644
>>>> --- a/target-arm/cpu.h
>>>> +++ b/target-arm/cpu.h
>>>> @@ -124,9 +124,9 @@ typedef struct CPUARMState {
>>>>       uint32_t spsr;
>>>>
>>>>       /* Banked registers.  */
>>>> -    uint32_t banked_spsr[6];
>>>> -    uint32_t banked_r13[6];
>>>> -    uint32_t banked_r14[6];
>>>> +    uint32_t banked_spsr[7];
>>>> +    uint32_t banked_r13[7];
>>>> +    uint32_t banked_r14[7];
>>>>
>>> Are there any more modes yet to be implemented? It might save on
>>> future VMSD version bumps if we just pad this out to its ultimate
>>> value now.
>>
>> The remaining mode defined for AArch32 which we don't
>> implement yet is Hyp mode, which has a banked R13 and SPSR,
>> but not a banked LR.
>>
>> -- PMM
>>
>>
>
> So should a number of banked core registers be increased more? Personally,
> I'd like to keep this patch only TZ-related.
>

So what im proposing is just a slightly more general patch. Is it
really any more complicated than just applying your change pattern for
the hyp mode? Patch subject would be something like:

"target-arm: Add all remaining missing modes"

The motiviation is less VMSD version bumps in ARM CPU (a place where I
expect assume such version bumps to be considerable annoyance).

Regards,
Peter

> Best regards,
> Sergey Fedorov
>