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[Qemu-devel] [PULL 19/24] sd/sdhci:ADMA: fix interrupt
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 19/24] sd/sdhci:ADMA: fix interrupt |
Date: |
Mon, 3 Jun 2013 17:30:16 +0100 |
From: Peter Crosthwaite <address@hidden>
The end of transfer check was occurring and potentially returning before
the interrupt flag was checked. This means the interrupt will be missed
if it occurs on the last packet. Fix by checking for the interrupt
before checking for the end of transfer.
Signed-off-by: Peter Crosthwaite <address@hidden>
Reviewed-by: Igor Mitsyanko <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
hw/sd/sdhci.c | 18 +++++++++---------
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
index 15345dc..e64899c 100644
--- a/hw/sd/sdhci.c
+++ b/hw/sd/sdhci.c
@@ -730,6 +730,15 @@ static void sdhci_do_adma(SDHCIState *s)
break;
}
+ if (dscr.attr & SDHC_ADMA_ATTR_INT) {
+ DPRINT_L1("ADMA interrupt: admasysaddr=0x%lx\n", s->admasysaddr);
+ if (s->norintstsen & SDHC_NISEN_DMA) {
+ s->norintsts |= SDHC_NIS_DMA;
+ }
+
+ sdhci_update_irq(s);
+ }
+
/* ADMA transfer terminates if blkcnt == 0 or by END attribute */
if (((s->trnmod & SDHC_TRNS_BLK_CNT_EN) &&
(s->blkcnt == 0)) || (dscr.attr & SDHC_ADMA_ATTR_END)) {
@@ -752,15 +761,6 @@ static void sdhci_do_adma(SDHCIState *s)
return;
}
- if (dscr.attr & SDHC_ADMA_ATTR_INT) {
- DPRINT_L1("ADMA interrupt: admasysaddr=0x%lx\n", s->admasysaddr);
- if (s->norintstsen & SDHC_NISEN_DMA) {
- s->norintsts |= SDHC_NIS_DMA;
- }
-
- sdhci_update_irq(s);
- return;
- }
}
/* we have unfinished business - reschedule to continue ADMA */
--
1.7.9.5
- [Qemu-devel] [PULL 00/24] arm-devs queue, Peter Maydell, 2013/06/03
- [Qemu-devel] [PULL 09/24] xilinx_spips: lqspi: Dont touch config register, Peter Maydell, 2013/06/03
- [Qemu-devel] [PULL 10/24] xilinx_spips: Fix CTRL register RW bits, Peter Maydell, 2013/06/03
- [Qemu-devel] [PULL 14/24] xilinx_spips: lqspi: Push more data to tx-fifo, Peter Maydell, 2013/06/03
- [Qemu-devel] [PULL 24/24] i.MX: Improve EPIT timer code., Peter Maydell, 2013/06/03
- [Qemu-devel] [PULL 12/24] xilinx_spips: Debug msgs for Snoop state, Peter Maydell, 2013/06/03
- [Qemu-devel] [PULL 13/24] xilinx_spips: Multiple debug verbosity levels, Peter Maydell, 2013/06/03
- [Qemu-devel] [PULL 06/24] xilinx_spips: Trash LQ page cache on mode change, Peter Maydell, 2013/06/03
- [Qemu-devel] [PULL 15/24] xilinx_spips: lqspi: Fix byte/misaligned access, Peter Maydell, 2013/06/03
- [Qemu-devel] [PULL 19/24] sd/sdhci:ADMA: fix interrupt,
Peter Maydell <=
- [Qemu-devel] [PULL 23/24] exynos4210.c: register rom_mem for memory migration, Peter Maydell, 2013/06/03
- [Qemu-devel] [PULL 16/24] sd/sdhci.c: Only reset data_count on new commands, Peter Maydell, 2013/06/03
- [Qemu-devel] [PULL 03/24] xilinx_spips: Inhibit interrupts in LQSPI mode, Peter Maydell, 2013/06/03
- [Qemu-devel] [PULL 05/24] xilinx_spips: Fix QSPI FIFO size, Peter Maydell, 2013/06/03
- [Qemu-devel] [PULL 04/24] xilinx_spips: Add verbose LQSPI debug output, Peter Maydell, 2013/06/03
- [Qemu-devel] [PULL 21/24] i.MX: split GPT and EPIT timer implementation, Peter Maydell, 2013/06/03
- [Qemu-devel] [PULL 17/24] sd/sdhci: Fix Buffer Write Ready interrupt, Peter Maydell, 2013/06/03
- [Qemu-devel] [PULL 08/24] xilinx_spips: Implement automatic CS, Peter Maydell, 2013/06/03
- [Qemu-devel] [PULL 22/24] hw/arm/exynos4210.c: convert chipid_and_omr to an mmio region, Peter Maydell, 2013/06/03
- [Qemu-devel] [PULL 02/24] xilinx_spips: Make interrupts clear on read, Peter Maydell, 2013/06/03