[Bug binutils/25202] objcopy --verilog-data-width doesn't respect target's endianness

[nickc at redhat dot com]

https://sourceware.org/bugzilla/show_bug.cgi?id=25202

--- Comment #17 from Nick Clifton <nickc at redhat dot com> ---
(Sorry for the delay in replying - I have been distracted by other work).

I think that we can avoid the alignment problem by insisting that for
widths greater than one, the section(s) being converted must already be 
aligned and padded to multiples of that width.

Hence, please could you try out the third iteration of the patch, which
should generate the correct address for widths > 1, and which will refuse
to convert unaligned sections.  I was not sure what to do about sections
which are not padded to the required alignment, so I have left the code
in its current form.  The code will just stop generating bytes when it
reaches the end of the section being converted and it will not generate
any padding bytes.

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