[Bug binutils/25202] objcopy --verilog-data-width doesn't respect target's endianness

[sourceware.org at aydos dot de]

https://sourceware.org/bugzilla/show_bug.cgi?id=25202

--- Comment #14 from Gökçe Aydos <sourceware.org at aydos dot de> ---
(In reply to Olof Kindgren from comment #13)
> ... we are dealing with word addresses, but are we taking that into
> consideration when we're calculating the base address?
> 
> I.e. compiling an asm program that starts with .org 0x100, will that cause
> the address to be set to @40 when using verilog-data-width=4 ?

Oh, I think that is the actual solution to the word addressing problem
(compared to my previous comment). Just shift the @addresses n =
log2(verilog-data-width) to the right, if they have n zeroes in the least
significant bits. If not, then they should be padded with zeroes.

> I believe that practically no one has actually used this feature much because 
> of this bug

I weakly remember that someone from the RISC-V community community hacked their
own C program to convert the .elf to a desired Verilog input format.

Thanks for chiming in Olof!

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