[Bug binutils/25202] objcopy --verilog-data-width doesn't respect target's endianness

[olof.kindgren at gmail dot com]

https://sourceware.org/bugzilla/show_bug.cgi?id=25202

--- Comment #21 from Olof Kindgren <olof.kindgren at gmail dot com> ---
Thanks for keeping working on this. I'm afraid I haven't had any time to test
it myself but it looks like we're on the right track. Yes, the data can be as
wide as it needs to be. There's probably some upper limit in the LRM but for
practical reasons I don't expect to hit that. I do see however that there could
be a use for e.g. 256-bit (data width = 32) wide memories as internal buses can
be that large and even 1024 bits and beyond on occasion.

I don't think that's a common case though, so I would personally be happy to
print a warning for widths > 16 and if someone is enough motivated to fix that,
they can do so separately. I'm reasonably sure that the vast majority will use
4 och 8 byte widths.

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