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Re: [Simulavr-devel] test mechanism
From: |
address@hidden |
Subject: |
Re: [Simulavr-devel] test mechanism |
Date: |
Wed, 19 Aug 2009 06:15:14 -0700 |
On Tue Aug 18 13:38 , "address@hidden" sent:
>On Tue Aug 18 11:47 , ThomasK address@hidden> sent:
>>Behaviour in simulavr is now like in M128, means read complete byte,
>>modify, write complete byte. For the new behaviour we need a new
>>interface for IO registers, one is clearBit(bitnum), the other
>>setBit(bitnum), not only read byte: operator char() and write byte:
>>operator=. And then, of course, for all the hardware units, which have
>>to provide this, not only a get and set method, but also a getbit/setbit
>>method or other modifybit(bitval, bitnum).
>
>I'd use the names sbi and cbi.
class RWMemoryMembers {
...
virtual unsigned char operator=(unsigned char val) =0;
#ifndef SWIG
virtual operator unsigned char() const =0 ;
virtual void sbi(unsigned bitnum) { *this= *this | (1<<bitnum); }
virtual void cbi(unsigned bitnum) { *this= *this & ~(1<<bitnum); }
#endif
...
};
I don't understand the need for #ifndef SWIG .
To list owner:
It would be nice if the list mechanism inserted a Reply-To: header line.
--
Michael Hennebry
address@hidden
"War is only a hobby."
---- Msg sent via CableONE.net MyMail - http://www.cableone.net
- Re: [Simulavr-devel] test mechanism, address@hidden, 2009/08/15
- Re: [Simulavr-devel] test mechanism, address@hidden, 2009/08/17
- Re: [Simulavr-devel] test mechanism, address@hidden, 2009/08/18
- Re: [Simulavr-devel] test mechanism,
address@hidden <=
- Re: [Simulavr-devel] test mechanism, address@hidden, 2009/08/19
- Re: [Simulavr-devel] test mechanism, address@hidden, 2009/08/19
- Re: [Simulavr-devel] test mechanism, address@hidden, 2009/08/20
- Re: [Simulavr-devel] test mechanism, address@hidden, 2009/08/21
- Re: [Simulavr-devel] test mechanism, address@hidden, 2009/08/25