Re: [Simulavr-devel] test mechanism

[address@hidden]

On Mon Aug 17 13:25 , ThomasK  sent:

>address@hidden schrieb:

>> Also, after  some  thought, I realized that my toggle
>> code would fail for SBI and CBI instructions.
>> It's probable that the original SBI and CBI
>> code would fail on the atmega{48,88,168}s.
>> On the atmega128, SBI and CBI are read byte, modify byte, write byte.
>> On the newer targets, SBI and CBI are read bit, modify bit, write bit.
>> The difference will show up when a relevant bit
>> is a flag bit that is cleared by  writing a one.
>> We need tests for SBI, CBI, IN, and OUT.
>
>Good idea, more good tests will improve the code. I have found the 
>double-free bug on extending the tests in regress/avrtest not only to 
>ATMega128, but also to other devices (AT90.., ATMega48)! :-) Maybe it's 
>not usefull to integrate tests for this menmonics into code tests from 
>regress.py. There are now some other test mechanisms: by python module 
>like in examples/python or over vcd dump like in regress/timertest 
>(there is only one test in the moment, I work hard to extend this and 
>make it more usefull ;-) )
>
>> Some of them need to depend on the CPU.
>
>Really? In my oppinion it's a variant of the port system? (but different 
>cpu's have different port systems link other hardware) I'll look in 
>datasheets, maybe I'm mistaken.

>From 7.5 I/O Memory of the 48/88/168 data sheet:
>Some of the Status Flags are cleared by writing a logical one to them. Note
that, unlike most
>other AVRs, the CBI and SBI instructions will only operate on the specified 
>bit,
and can therefore
>be used on registers containing such Status Flags.

CBI and SBI will work differently on the 128.
On the 128, an SBI would clear all the status flags.
On the 128, a CBI would clear all the status flags except the one specified.
It's an effect of only writing whole bytes.

Of course, even the ports corresponding to pins have different availabilities.

--
Michael Hennebry
address@hidden
"War is only a hobby."
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