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Re: [Qemu-devel] [PATCH v2 23/29] target/riscv: Move gen_arith_imm() dec
From: |
Richard Henderson |
Subject: |
Re: [Qemu-devel] [PATCH v2 23/29] target/riscv: Move gen_arith_imm() decoding into trans_* functions |
Date: |
Tue, 23 Oct 2018 09:46:09 +0100 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.2.1 |
On 10/20/18 8:14 AM, Bastian Koppelmann wrote:
> static bool trans_srli(DisasContext *ctx, arg_srli *a, uint32_t insn)
> {
> - gen_arith_imm(ctx, OPC_RISC_SHIFT_RIGHT_I, a->rd, a->rs1, a->shamt);
> + if (a->rd != 0) {
> + TCGv t = tcg_temp_new();
> + gen_get_gpr(t, a->rs1);
> + tcg_gen_extract_tl(t, t, a->shamt, 64 - a->shamt);
tcg_gen_shri_tl(t, t, a->shamt);
This is a mis-translation of the original code which handled srliw too.
You should be able to see this assert on riscv32.
> static bool trans_srai(DisasContext *ctx, arg_srai *a, uint32_t insn)
> {
> - gen_arith_imm(ctx, OPC_RISC_SHIFT_RIGHT_I, a->rd, a->rs1, a->shamt |
> 0x400);
> + if (a->rd != 0) {
> + TCGv t = tcg_temp_new();
> + gen_get_gpr(t, a->rs1);
> + tcg_gen_sextract_tl(t, t, a->shamt, 64 - a->shamt);
Similarly.
r~
- [Qemu-devel] [PATCH v2 28/29] target/riscv: Remove decode_RV32_64G(), (continued)
- [Qemu-devel] [PATCH v2 28/29] target/riscv: Remove decode_RV32_64G(), Bastian Koppelmann, 2018/10/20
- [Qemu-devel] [PATCH v2 21/29] target/riscv: Remove manual decoding from gen_load(), Bastian Koppelmann, 2018/10/20
- [Qemu-devel] [PATCH v2 25/29] target/riscv: Remove shift and slt insn manual decoding, Bastian Koppelmann, 2018/10/20
- [Qemu-devel] [PATCH v2 27/29] target/riscv: Remove gen_system(), Bastian Koppelmann, 2018/10/20
- [Qemu-devel] [PATCH v2 20/29] target/riscv: Remove manual decoding from gen_branch(), Bastian Koppelmann, 2018/10/20
- [Qemu-devel] [PATCH v2 22/29] target/riscv: Remove manual decoding from gen_store(), Bastian Koppelmann, 2018/10/20
- [Qemu-devel] [PATCH v2 29/29] target/riscv: Rename trans_arith to gen_arith, Bastian Koppelmann, 2018/10/20
- [Qemu-devel] [PATCH v2 23/29] target/riscv: Move gen_arith_imm() decoding into trans_* functions, Bastian Koppelmann, 2018/10/20
- [Qemu-devel] [PATCH v2 24/29] target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists, Bastian Koppelmann, 2018/10/20
- [Qemu-devel] [PATCH v2 26/29] target/riscv: Remove manual decoding of RV32/64M insn, Bastian Koppelmann, 2018/10/20
- Re: [Qemu-devel] [PATCH v2 00/29] target/riscv: Convert to decodetree, Palmer Dabbelt, 2018/10/24