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[Qemu-devel] [PATCH v2 29/29] target/riscv: Rename trans_arith to gen_ar
From: |
Bastian Koppelmann |
Subject: |
[Qemu-devel] [PATCH v2 29/29] target/riscv: Rename trans_arith to gen_arith |
Date: |
Sat, 20 Oct 2018 09:14:51 +0200 |
Signed-off-by: Bastian Koppelmann <address@hidden>
---
target/riscv/insn_trans/trans_rvi.inc.c | 14 +++++++-------
target/riscv/insn_trans/trans_rvm.inc.c | 14 +++++++-------
target/riscv/translate.c | 4 ++--
3 files changed, 16 insertions(+), 16 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvi.inc.c
b/target/riscv/insn_trans/trans_rvi.inc.c
index 5ece5e2f6a..0455f0bf91 100644
--- a/target/riscv/insn_trans/trans_rvi.inc.c
+++ b/target/riscv/insn_trans/trans_rvi.inc.c
@@ -315,12 +315,12 @@ static bool trans_srai(DisasContext *ctx, arg_srai *a,
uint32_t insn)
static bool trans_add(DisasContext *ctx, arg_add *a, uint32_t insn)
{
- return trans_arith(ctx, a, &tcg_gen_add_tl);
+ return gen_arith(ctx, a, &tcg_gen_add_tl);
}
static bool trans_sub(DisasContext *ctx, arg_sub *a, uint32_t insn)
{
- return trans_arith(ctx, a, &tcg_gen_sub_tl);
+ return gen_arith(ctx, a, &tcg_gen_sub_tl);
}
static bool trans_sll(DisasContext *ctx, arg_sll *a, uint32_t insn)
@@ -363,7 +363,7 @@ static bool trans_sltu(DisasContext *ctx, arg_sltu *a,
uint32_t insn)
static bool trans_xor(DisasContext *ctx, arg_xor *a, uint32_t insn)
{
- return trans_arith(ctx, a, &tcg_gen_xor_tl);
+ return gen_arith(ctx, a, &tcg_gen_xor_tl);
}
@@ -379,12 +379,12 @@ static bool trans_sra(DisasContext *ctx, arg_sra *a,
uint32_t insn)
static bool trans_or(DisasContext *ctx, arg_or *a, uint32_t insn)
{
- return trans_arith(ctx, a, &tcg_gen_or_tl);
+ return gen_arith(ctx, a, &tcg_gen_or_tl);
}
static bool trans_and(DisasContext *ctx, arg_and *a, uint32_t insn)
{
- return trans_arith(ctx, a, &tcg_gen_and_tl);
+ return gen_arith(ctx, a, &tcg_gen_and_tl);
}
static bool trans_addiw(DisasContext *ctx, arg_addiw *a, uint32_t insn)
@@ -453,7 +453,7 @@ static bool trans_addw(DisasContext *ctx, arg_addw *a,
uint32_t insn)
#if !defined(TARGET_RISCV64)
return false;
#endif
- return trans_arith(ctx, a, &tcg_gen_add_tl);
+ return gen_arith(ctx, a, &tcg_gen_add_tl);
}
static bool trans_subw(DisasContext *ctx, arg_subw *a, uint32_t insn)
@@ -461,7 +461,7 @@ static bool trans_subw(DisasContext *ctx, arg_subw *a,
uint32_t insn)
#if !defined(TARGET_RISCV64)
return false;
#endif
- return trans_arith(ctx, a, &tcg_gen_sub_tl);
+ return gen_arith(ctx, a, &tcg_gen_sub_tl);
}
static bool trans_sllw(DisasContext *ctx, arg_sllw *a, uint32_t insn)
diff --git a/target/riscv/insn_trans/trans_rvm.inc.c
b/target/riscv/insn_trans/trans_rvm.inc.c
index 93859745b8..0bc9b4347a 100644
--- a/target/riscv/insn_trans/trans_rvm.inc.c
+++ b/target/riscv/insn_trans/trans_rvm.inc.c
@@ -21,7 +21,7 @@
static bool trans_mul(DisasContext *ctx, arg_mul *a, uint32_t insn)
{
- return trans_arith(ctx, a, &tcg_gen_mul_tl);
+ return gen_arith(ctx, a, &tcg_gen_mul_tl);
}
static bool trans_mulh(DisasContext *ctx, arg_mulh *a, uint32_t insn)
@@ -41,7 +41,7 @@ static bool trans_mulh(DisasContext *ctx, arg_mulh *a,
uint32_t insn)
static bool trans_mulhsu(DisasContext *ctx, arg_mulhsu *a, uint32_t insn)
{
- return trans_arith(ctx, a, &gen_mulhsu);
+ return gen_arith(ctx, a, &gen_mulhsu);
}
static bool trans_mulhu(DisasContext *ctx, arg_mulhu *a, uint32_t insn)
@@ -61,28 +61,28 @@ static bool trans_mulhu(DisasContext *ctx, arg_mulhu *a,
uint32_t insn)
static bool trans_div(DisasContext *ctx, arg_div *a, uint32_t insn)
{
- return trans_arith(ctx, a, &gen_div);
+ return gen_arith(ctx, a, &gen_div);
}
static bool trans_divu(DisasContext *ctx, arg_divu *a, uint32_t insn)
{
- return trans_arith(ctx, a, &gen_divu);
+ return gen_arith(ctx, a, &gen_divu);
}
static bool trans_rem(DisasContext *ctx, arg_rem *a, uint32_t insn)
{
- return trans_arith(ctx, a, &gen_rem);
+ return gen_arith(ctx, a, &gen_rem);
}
static bool trans_remu(DisasContext *ctx, arg_remu *a, uint32_t insn)
{
- return trans_arith(ctx, a, &gen_remu);
+ return gen_arith(ctx, a, &gen_remu);
}
static bool trans_mulw(DisasContext *ctx, arg_mulw *a, uint32_t insn)
{
#ifdef TARGET_RISCV64
- return trans_arith(ctx, a, &tcg_gen_mul_tl);
+ return gen_arith(ctx, a, &tcg_gen_mul_tl);
#else
return false;
#endif
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 66241ecf33..ece163e69f 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -344,8 +344,8 @@ static bool gen_arith_imm(DisasContext *ctx, arg_arith_imm
*a,
return true;
}
-static bool trans_arith(DisasContext *ctx, arg_arith *a,
- void(*func)(TCGv, TCGv, TCGv))
+static bool gen_arith(DisasContext *ctx, arg_arith *a,
+ void(*func)(TCGv, TCGv, TCGv))
{
TCGv source1, source2;
source1 = tcg_temp_new();
--
2.19.1
- [Qemu-devel] [PATCH v2 19/29] target/riscv: Remove gen_jalr(), (continued)
- [Qemu-devel] [PATCH v2 19/29] target/riscv: Remove gen_jalr(), Bastian Koppelmann, 2018/10/20
- [Qemu-devel] [PATCH v2 18/29] target/riscv: Convert quadrant 2 of RVXC insns to decodetree, Bastian Koppelmann, 2018/10/20
- [Qemu-devel] [PATCH v2 28/29] target/riscv: Remove decode_RV32_64G(), Bastian Koppelmann, 2018/10/20
- [Qemu-devel] [PATCH v2 21/29] target/riscv: Remove manual decoding from gen_load(), Bastian Koppelmann, 2018/10/20
- [Qemu-devel] [PATCH v2 25/29] target/riscv: Remove shift and slt insn manual decoding, Bastian Koppelmann, 2018/10/20
- [Qemu-devel] [PATCH v2 27/29] target/riscv: Remove gen_system(), Bastian Koppelmann, 2018/10/20
- [Qemu-devel] [PATCH v2 20/29] target/riscv: Remove manual decoding from gen_branch(), Bastian Koppelmann, 2018/10/20
- [Qemu-devel] [PATCH v2 22/29] target/riscv: Remove manual decoding from gen_store(), Bastian Koppelmann, 2018/10/20
- [Qemu-devel] [PATCH v2 29/29] target/riscv: Rename trans_arith to gen_arith,
Bastian Koppelmann <=
- [Qemu-devel] [PATCH v2 23/29] target/riscv: Move gen_arith_imm() decoding into trans_* functions, Bastian Koppelmann, 2018/10/20
- [Qemu-devel] [PATCH v2 24/29] target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists, Bastian Koppelmann, 2018/10/20
- [Qemu-devel] [PATCH v2 26/29] target/riscv: Remove manual decoding of RV32/64M insn, Bastian Koppelmann, 2018/10/20
- Re: [Qemu-devel] [PATCH v2 00/29] target/riscv: Convert to decodetree, Palmer Dabbelt, 2018/10/24