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[Qemu-devel] [PATCH v5 3/9] i386: Initialize cache information for EPYC
From: |
Babu Moger |
Subject: |
[Qemu-devel] [PATCH v5 3/9] i386: Initialize cache information for EPYC family processors |
Date: |
Tue, 27 Mar 2018 17:31:05 -0400 |
Initialize pre-determined cache information for EPYC processors.
Signed-off-by: Babu Moger <address@hidden>
---
target/i386/cpu.c | 96 +++++++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 96 insertions(+)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index eec4a97..67faa53 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -2299,6 +2299,54 @@ static X86CPUDefinition builtin_x86_defs[] = {
CPUID_6_EAX_ARAT,
.xlevel = 0x8000000A,
.model_id = "AMD EPYC Processor",
+ .cache_info.valid = 1,
+ .cache_info.l1d_cache = {
+ .type = DCACHE,
+ .level = 1,
+ .size = 32 * KiB,
+ .line_size = 64,
+ .associativity = 8,
+ .partitions = 1,
+ .sets = 64,
+ .lines_per_tag = 1,
+ .self_init = 1,
+ .no_invd_sharing = true,
+ },
+ .cache_info.l1i_cache = {
+ .type = ICACHE,
+ .level = 1,
+ .size = 64 * KiB,
+ .line_size = 64,
+ .associativity = 4,
+ .partitions = 1,
+ .sets = 256,
+ .lines_per_tag = 1,
+ .self_init = 1,
+ .no_invd_sharing = true,
+ },
+ .cache_info.l2_cache = {
+ .type = UNIFIED_CACHE,
+ .level = 2,
+ .size = 512 * KiB,
+ .line_size = 64,
+ .associativity = 8,
+ .partitions = 1,
+ .sets = 1024,
+ .lines_per_tag = 1,
+ },
+ .cache_info.l3_cache = {
+ .type = UNIFIED_CACHE,
+ .level = 3,
+ .size = 16 * MiB,
+ .line_size = 64,
+ .associativity = 16,
+ .partitions = 1,
+ .sets = 16384,
+ .lines_per_tag = 1,
+ .self_init = true,
+ .inclusive = true,
+ .complex_indexing = true,
+ },
},
{
.name = "EPYC-IBPB",
@@ -2345,6 +2393,54 @@ static X86CPUDefinition builtin_x86_defs[] = {
CPUID_6_EAX_ARAT,
.xlevel = 0x8000000A,
.model_id = "AMD EPYC Processor (with IBPB)",
+ .cache_info.valid = 1,
+ .cache_info.l1d_cache = {
+ .type = DCACHE,
+ .level = 1,
+ .size = 32 * KiB,
+ .line_size = 64,
+ .associativity = 8,
+ .partitions = 1,
+ .sets = 64,
+ .lines_per_tag = 1,
+ .self_init = 1,
+ .no_invd_sharing = true,
+ },
+ .cache_info.l1i_cache = {
+ .type = ICACHE,
+ .level = 1,
+ .size = 64 * KiB,
+ .line_size = 64,
+ .associativity = 4,
+ .partitions = 1,
+ .sets = 256,
+ .lines_per_tag = 1,
+ .self_init = 1,
+ .no_invd_sharing = true,
+ },
+ .cache_info.l2_cache = {
+ .type = UNIFIED_CACHE,
+ .level = 2,
+ .size = 512 * KiB,
+ .line_size = 64,
+ .associativity = 8,
+ .partitions = 1,
+ .sets = 1024,
+ .lines_per_tag = 1,
+ },
+ .cache_info.l3_cache = {
+ .type = UNIFIED_CACHE,
+ .level = 3,
+ .size = 16 * MiB,
+ .line_size = 64,
+ .associativity = 16,
+ .partitions = 1,
+ .sets = 16384,
+ .lines_per_tag = 1,
+ .self_init = true,
+ .inclusive = true,
+ .complex_indexing = true,
+ },
},
};
--
1.8.3.1
- [Qemu-devel] [PATCH v5 0/9] i386: Enable TOPOEXT to support hyperthreading on AMD CPU, Babu Moger, 2018/03/27
- [Qemu-devel] [PATCH v5 2/9] i386: Add cache information in X86CPUDefinition, Babu Moger, 2018/03/27
- [Qemu-devel] [PATCH v5 3/9] i386: Initialize cache information for EPYC family processors,
Babu Moger <=
- [Qemu-devel] [PATCH v5 5/9] i386: Use the statically loaded cache definitions, Babu Moger, 2018/03/27
- [Qemu-devel] [PATCH v5 1/9] i386: Helpers to encode cache information consistently, Babu Moger, 2018/03/27
- [Qemu-devel] [PATCH v5 4/9] i386: Add new property to control cache info, Babu Moger, 2018/03/27
- [Qemu-devel] [PATCH v5 6/9] i386: Populate AMD Processor Cache Information for cpuid 0x8000001D, Babu Moger, 2018/03/27
- [Qemu-devel] [PATCH v5 8/9] i386: Enable TOPOEXT feature on AMD EPYC CPU, Babu Moger, 2018/03/27
- [Qemu-devel] [PATCH v5 9/9] i386: Remove generic SMT thread check, Babu Moger, 2018/03/27
- [Qemu-devel] [PATCH v5 7/9] i386: Add support for CPUID_8000_001E for AMD, Babu Moger, 2018/03/27