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[Qemu-devel] [PATCH v5 5/9] i386: Use the statically loaded cache defini
From: |
Babu Moger |
Subject: |
[Qemu-devel] [PATCH v5 5/9] i386: Use the statically loaded cache definitions |
Date: |
Tue, 27 Mar 2018 17:31:07 -0400 |
Use the statically loaded cache definitions if available
and legacy-cache parameter is not set.
Signed-off-by: Babu Moger <address@hidden>
---
target/i386/cpu.c | 22 +++++++++++++++++-----
1 file changed, 17 insertions(+), 5 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index f4fbe3a..738927d 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -3938,8 +3938,13 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index,
uint32_t count,
(L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES);
*ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | \
(L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES);
- *ecx = encode_cache_cpuid80000005(&l1d_cache_amd);
- *edx = encode_cache_cpuid80000005(&l1i_cache_amd);
+ if (env->cache_info.valid && !cpu->legacy_cache) {
+ *ecx = encode_cache_cpuid80000005(&env->cache_info.l1d_cache);
+ *edx = encode_cache_cpuid80000005(&env->cache_info.l1i_cache);
+ } else {
+ *ecx = encode_cache_cpuid80000005(&l1d_cache_amd);
+ *edx = encode_cache_cpuid80000005(&l1i_cache_amd);
+ }
break;
case 0x80000006:
/* cache info (L2 cache) */
@@ -3955,9 +3960,16 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index,
uint32_t count,
(L2_DTLB_4K_ENTRIES << 16) | \
(AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | \
(L2_ITLB_4K_ENTRIES);
- encode_cache_cpuid80000006(&l2_cache_amd,
- cpu->enable_l3_cache ? &l3_cache : NULL,
- ecx, edx);
+ if (env->cache_info.valid && !cpu->legacy_cache) {
+ encode_cache_cpuid80000006(&env->cache_info.l2_cache,
+ cpu->enable_l3_cache ?
+ &env->cache_info.l3_cache : NULL,
+ ecx, edx);
+ } else {
+ encode_cache_cpuid80000006(&l2_cache_amd,
+ cpu->enable_l3_cache ? &l3_cache : NULL,
+ ecx, edx);
+ }
break;
case 0x80000007:
*eax = 0;
--
1.8.3.1
- [Qemu-devel] [PATCH v5 0/9] i386: Enable TOPOEXT to support hyperthreading on AMD CPU, Babu Moger, 2018/03/27
- [Qemu-devel] [PATCH v5 2/9] i386: Add cache information in X86CPUDefinition, Babu Moger, 2018/03/27
- [Qemu-devel] [PATCH v5 3/9] i386: Initialize cache information for EPYC family processors, Babu Moger, 2018/03/27
- [Qemu-devel] [PATCH v5 5/9] i386: Use the statically loaded cache definitions,
Babu Moger <=
- [Qemu-devel] [PATCH v5 1/9] i386: Helpers to encode cache information consistently, Babu Moger, 2018/03/27
- [Qemu-devel] [PATCH v5 4/9] i386: Add new property to control cache info, Babu Moger, 2018/03/27
- [Qemu-devel] [PATCH v5 6/9] i386: Populate AMD Processor Cache Information for cpuid 0x8000001D, Babu Moger, 2018/03/27
- [Qemu-devel] [PATCH v5 8/9] i386: Enable TOPOEXT feature on AMD EPYC CPU, Babu Moger, 2018/03/27
- [Qemu-devel] [PATCH v5 9/9] i386: Remove generic SMT thread check, Babu Moger, 2018/03/27
- [Qemu-devel] [PATCH v5 7/9] i386: Add support for CPUID_8000_001E for AMD, Babu Moger, 2018/03/27