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Re: [Qemu-devel] [PATCH 03/29] target-sparc: add UA2005 TTE bit #defines


From: Artyom Tarasenko
Subject: Re: [Qemu-devel] [PATCH 03/29] target-sparc: add UA2005 TTE bit #defines
Date: Wed, 12 Oct 2016 13:18:05 +0200

On Tue, Oct 11, 2016 at 5:08 PM, Richard Henderson <address@hidden> wrote:
> On 10/11/2016 08:51 AM, Artyom Tarasenko wrote:
>>
>> On Tue, Oct 11, 2016 at 7:50 AM, Richard Henderson <address@hidden>
>> wrote:
>>>
>>> On 10/10/2016 04:45 PM, Artyom Tarasenko wrote:
>>>>>
>>>>>
>>>>> Hmm.  Would it make more sense to reorg these as
>>>>>
>>>>>   TTE_US1_*
>>>>>   TTE_UA2005_*
>>>>>
>>>>> with some duplication for the bits that are shared?
>>>>> As is, it's pretty hard to tell which actually change...
>>>>
>>>>
>>>>
>>>> All of them :-)
>>>> I'm not sure about renaming: the US1 format is still used in T1 on the
>>>> read
>>>> access.
>>>>
>>>> On the other hand, it's not used in T2. And then again we don't have the
>>>> T2
>>>> emulation yet.
>>>
>>>
>>>
>>> Oh my.  Different on T2 as well?
>>
>>
>> T2 has more used bits, and can not use the US1 format, I think.
>>
>>> I wonder if it would make sense to have different functions with which to
>>> fill in the CPUClass hooks (or invent new SPARCCPUClass hooks as
>>> necessary)
>>> for the major entry points.
>>>
>>> E.g. sparc_cpu_handle_mmu_fault or get_physical_address could be hooked,
>>> so
>>> that the choice of how to handle the tlb miss is chosen at startup time,
>>> and
>>> not during each fault.  One can arrange subroutines as necessary to share
>>> code between the alternate routines, such as when T1 needs to use parts
>>> of
>>> US1.
>>
>>
>> Yes, I plan to do it once I get to T2 emulation.
>
>
> Ok.
>
>>> Similarly for out-of-line ASI handling, which is already beyond messy,
>>> with
>>> handling for all cpus thrown in the same switch statement.
>>
>>
>> Yes. I think we need to split SPARCv9 standard ASIs from CPU-specific
>> ones, call cpu-specific handlers first and standard handler
>> afterwards.
>> But not in this series.
>
>
> Fair enough.
>
> What I would most like to see, for QEMU, is an artificial sun4v compatible
> machine that implements a "hardware" page table walk.  I.e. no use of
> SparcTLBEntry, but walking the page tables directly.
>
> Because QEMU can then satisfy a page lookup internally, without having to
> longjmp out of a memory reference in progress in order to restart the cpu
> for the software TLB miss handler, the emulation runs about 30-50% faster.
> At least that has been my experience emulating Alpha vs MIPS.
>
> It would require custom roms, but those should be fairly easy to modify from
> the existing source.
>

Maybe it's even possible without the modifications. For instance,
implement the table walk compatible with the current hypervisor, and
then just add possibility to overlay hypervisor call using some CPU
feature flag.


-- 
Regards,
Artyom Tarasenko

SPARC and PPC PReP under qemu blog: http://tyom.blogspot.com/search/label/qemu



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