Re: [Qemu-devel] [PATCH 03/29] target-sparc: add UA2005 TTE bit #defines

[Richard Henderson]

On 10/12/2016 06:18 AM, Artyom Tarasenko wrote:
> > What I would most like to see, for QEMU, is an artificial sun4v compatible
> > machine that implements a "hardware" page table walk.  I.e. no use of
> > SparcTLBEntry, but walking the page tables directly.
> >
> > Because QEMU can then satisfy a page lookup internally, without having to
> > longjmp out of a memory reference in progress in order to restart the cpu
> > for the software TLB miss handler, the emulation runs about 30-50% faster.
> > At least that has been my experience emulating Alpha vs MIPS.
> >
> > It would require custom roms, but those should be fairly easy to modify from
> > the existing source.
>
> Maybe it's even possible without the modifications. For instance,
> implement the table walk compatible with the current hypervisor, and
> then just add possibility to overlay hypervisor call using some CPU
> feature flag.

Maybe so.  What we lack is being given direct access to the page table base. 
But we know that the CPU structure is in the hypervisor shadow register 0, and 
that offset CPU_ROOT is the page table base.

As long as we're willing to hard-code these two facts concerning any rom we 
care to load, we could in fact implement the tlb miss success path inside QEMU. 
 We would let the rom re-do the work for the tlb miss failure path, on the way 
to raising the exception with the supervisor.


r~