[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PATCH v3 01/11] target-arm: Share all common TCG temporari
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH v3 01/11] target-arm: Share all common TCG temporaries |
Date: |
Thu, 10 Sep 2015 11:18:13 -0700 |
This is a bug fix for aarch64. At present, we have branches using
the 32-bit (translate.c) versions of cpu_[NZCV]F, but we set the flags
using the 64-bit (translate-a64.c) versions of cpu_[NZCV]F. From
the view of the TCG code generator, these are unrelated variables.
The bug is hard to see because we currently only read these variables
from branches, and upon reaching a branch TCG will first spill live
variables and then reload the arguments of the branch. Since the
32-bit versions were never live until reaching the branch, we'd re-read
the data that had just been spilled from the 64-bit versions.
There is currently no such problem with the cpu_exclusive_* variables,
but there's no point in tempting fate.
Cc: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
target-arm/translate-a64.c | 22 ----------------------
target-arm/translate.c | 10 +++++-----
target-arm/translate.h | 8 ++++++++
3 files changed, 13 insertions(+), 27 deletions(-)
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index 529bb0c..342bdbd 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -40,16 +40,9 @@
static TCGv_i64 cpu_X[32];
static TCGv_i64 cpu_pc;
-static TCGv_i32 cpu_NF, cpu_ZF, cpu_CF, cpu_VF;
/* Load/store exclusive handling */
-static TCGv_i64 cpu_exclusive_addr;
-static TCGv_i64 cpu_exclusive_val;
static TCGv_i64 cpu_exclusive_high;
-#ifdef CONFIG_USER_ONLY
-static TCGv_i64 cpu_exclusive_test;
-static TCGv_i32 cpu_exclusive_info;
-#endif
static const char *regnames[] = {
"x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
@@ -105,23 +98,8 @@ void a64_translate_init(void)
regnames[i]);
}
- cpu_NF = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUARMState, NF),
"NF");
- cpu_ZF = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUARMState, ZF),
"ZF");
- cpu_CF = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUARMState, CF),
"CF");
- cpu_VF = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUARMState, VF),
"VF");
-
- cpu_exclusive_addr = tcg_global_mem_new_i64(TCG_AREG0,
- offsetof(CPUARMState, exclusive_addr), "exclusive_addr");
- cpu_exclusive_val = tcg_global_mem_new_i64(TCG_AREG0,
- offsetof(CPUARMState, exclusive_val), "exclusive_val");
cpu_exclusive_high = tcg_global_mem_new_i64(TCG_AREG0,
offsetof(CPUARMState, exclusive_high), "exclusive_high");
-#ifdef CONFIG_USER_ONLY
- cpu_exclusive_test = tcg_global_mem_new_i64(TCG_AREG0,
- offsetof(CPUARMState, exclusive_test), "exclusive_test");
- cpu_exclusive_info = tcg_global_mem_new_i32(TCG_AREG0,
- offsetof(CPUARMState, exclusive_info), "exclusive_info");
-#endif
}
static inline ARMMMUIdx get_a64_user_mem_index(DisasContext *s)
diff --git a/target-arm/translate.c b/target-arm/translate.c
index e27634f..3826a02 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -64,12 +64,12 @@ TCGv_ptr cpu_env;
/* We reuse the same 64-bit temporaries for efficiency. */
static TCGv_i64 cpu_V0, cpu_V1, cpu_M0;
static TCGv_i32 cpu_R[16];
-static TCGv_i32 cpu_CF, cpu_NF, cpu_VF, cpu_ZF;
-static TCGv_i64 cpu_exclusive_addr;
-static TCGv_i64 cpu_exclusive_val;
+TCGv_i32 cpu_CF, cpu_NF, cpu_VF, cpu_ZF;
+TCGv_i64 cpu_exclusive_addr;
+TCGv_i64 cpu_exclusive_val;
#ifdef CONFIG_USER_ONLY
-static TCGv_i64 cpu_exclusive_test;
-static TCGv_i32 cpu_exclusive_info;
+TCGv_i64 cpu_exclusive_test;
+TCGv_i32 cpu_exclusive_info;
#endif
/* FIXME: These should be removed. */
diff --git a/target-arm/translate.h b/target-arm/translate.h
index 9ab978f..679bdbc 100644
--- a/target-arm/translate.h
+++ b/target-arm/translate.h
@@ -62,7 +62,15 @@ typedef struct DisasContext {
TCGv_i64 tmp_a64[TMP_A64_MAX];
} DisasContext;
+/* Share the TCG temporaries common between 32 and 64 bit modes. */
extern TCGv_ptr cpu_env;
+extern TCGv_i32 cpu_NF, cpu_ZF, cpu_CF, cpu_VF;
+extern TCGv_i64 cpu_exclusive_addr;
+extern TCGv_i64 cpu_exclusive_val;
+#ifdef CONFIG_USER_ONLY
+extern TCGv_i64 cpu_exclusive_test;
+extern TCGv_i32 cpu_exclusive_info;
+#endif
static inline int arm_dc_feature(DisasContext *dc, int feature)
{
--
2.4.3
- [Qemu-devel] [PATCH v3 00/11] target-arm improvments for aarch64, Richard Henderson, 2015/09/10
- [Qemu-devel] [PATCH v3 03/11] target-arm: Handle always condition codes within arm_test_cc, Richard Henderson, 2015/09/10
- [Qemu-devel] [PATCH v3 02/11] target-arm: Introduce DisasCompare, Richard Henderson, 2015/09/10
- [Qemu-devel] [PATCH v3 01/11] target-arm: Share all common TCG temporaries,
Richard Henderson <=
- [Qemu-devel] [PATCH v3 04/11] target-arm: Use setcond and movcond for csel, Richard Henderson, 2015/09/10
- [Qemu-devel] [PATCH v3 07/11] target-arm: Recognize SXTB, SXTH, SXTW, ASR, Richard Henderson, 2015/09/10
- [Qemu-devel] [PATCH v3 08/11] target-arm: Recognize UXTB, UXTH, LSR, LSL, Richard Henderson, 2015/09/10
- [Qemu-devel] [PATCH v3 05/11] target-arm: Implement ccmp branchless, Richard Henderson, 2015/09/10
- [Qemu-devel] [PATCH v3 09/11] target-arm: Eliminate unnecessary zero-extend in disas_bitfield, Richard Henderson, 2015/09/10
- [Qemu-devel] [PATCH v3 11/11] target-arm: Use tcg_gen_extrh_i64_i32, Richard Henderson, 2015/09/10
- [Qemu-devel] [PATCH v3 06/11] target-arm: Implement fcsel with movcond, Richard Henderson, 2015/09/10
- [Qemu-devel] [PATCH v3 10/11] target-arm: Recognize ROR, Richard Henderson, 2015/09/10
- Re: [Qemu-devel] [PATCH v3 00/11] target-arm improvments for aarch64, Peter Maydell, 2015/09/11