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[Qemu-devel] [PATCH v3 09/11] target-arm: Eliminate unnecessary zero-ext
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH v3 09/11] target-arm: Eliminate unnecessary zero-extend in disas_bitfield |
Date: |
Thu, 10 Sep 2015 11:18:21 -0700 |
For !SF, this initial ext32u can't be optimized away by the
current TCG code generator. (It would require backward bit
liveness propagation.)
But since the range of bits for !SF are already constrained by
unallocated_encoding, we'll never reference the high bits anyway.
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
target-arm/translate-a64.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index cf68754..56aa043 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -3015,7 +3015,11 @@ static void disas_bitfield(DisasContext *s, uint32_t
insn)
}
tcg_rd = cpu_reg(s, rd);
- tcg_tmp = read_cpu_reg(s, rn, sf);
+
+ /* Suppress the zero-extend for !sf. Since RI and SI are constrained
+ to be smaller than bitsize, we'll never reference data outside the
+ low 32-bits anyway. */
+ tcg_tmp = read_cpu_reg(s, rn, 1);
/* Recognize the common aliases. */
if (opc == 0) { /* SBFM */
--
2.4.3
- [Qemu-devel] [PATCH v3 00/11] target-arm improvments for aarch64, Richard Henderson, 2015/09/10
- [Qemu-devel] [PATCH v3 03/11] target-arm: Handle always condition codes within arm_test_cc, Richard Henderson, 2015/09/10
- [Qemu-devel] [PATCH v3 02/11] target-arm: Introduce DisasCompare, Richard Henderson, 2015/09/10
- [Qemu-devel] [PATCH v3 01/11] target-arm: Share all common TCG temporaries, Richard Henderson, 2015/09/10
- [Qemu-devel] [PATCH v3 04/11] target-arm: Use setcond and movcond for csel, Richard Henderson, 2015/09/10
- [Qemu-devel] [PATCH v3 07/11] target-arm: Recognize SXTB, SXTH, SXTW, ASR, Richard Henderson, 2015/09/10
- [Qemu-devel] [PATCH v3 08/11] target-arm: Recognize UXTB, UXTH, LSR, LSL, Richard Henderson, 2015/09/10
- [Qemu-devel] [PATCH v3 05/11] target-arm: Implement ccmp branchless, Richard Henderson, 2015/09/10
- [Qemu-devel] [PATCH v3 09/11] target-arm: Eliminate unnecessary zero-extend in disas_bitfield,
Richard Henderson <=
- [Qemu-devel] [PATCH v3 11/11] target-arm: Use tcg_gen_extrh_i64_i32, Richard Henderson, 2015/09/10
- [Qemu-devel] [PATCH v3 06/11] target-arm: Implement fcsel with movcond, Richard Henderson, 2015/09/10
- [Qemu-devel] [PATCH v3 10/11] target-arm: Recognize ROR, Richard Henderson, 2015/09/10
- Re: [Qemu-devel] [PATCH v3 00/11] target-arm improvments for aarch64, Peter Maydell, 2015/09/11