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[Qemu-devel] [PATCH v3 03/11] target-arm: Handle always condition codes
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH v3 03/11] target-arm: Handle always condition codes within arm_test_cc |
Date: |
Thu, 10 Sep 2015 11:18:15 -0700 |
Handling this with TCG_COND_ALWAYS will allow these unlikely
cases to be handled without special cases in the rest of the
translator. The TCG optimizer ought to be able to reduce
these ALWAYS conditions completely.
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
target-arm/translate.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/target-arm/translate.c b/target-arm/translate.c
index 52452cf..3e7c367 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -804,6 +804,14 @@ void arm_test_cc(DisasCompare *cmp, int cc)
tcg_gen_andc_i32(value, cpu_ZF, value);
break;
+ case 14: /* always */
+ case 15: /* always */
+ /* Use the ALWAYS condition, which will fold early.
+ * It doesn't matter what we use for the value. */
+ cond = TCG_COND_ALWAYS;
+ value = cpu_ZF;
+ goto no_invert;
+
default:
fprintf(stderr, "Bad condition code 0x%x\n", cc);
abort();
@@ -813,6 +821,7 @@ void arm_test_cc(DisasCompare *cmp, int cc)
cond = tcg_invert_cond(cond);
}
+ no_invert:
cmp->cond = cond;
cmp->value = value;
cmp->value_global = global;
--
2.4.3
- [Qemu-devel] [PATCH v3 00/11] target-arm improvments for aarch64, Richard Henderson, 2015/09/10
- [Qemu-devel] [PATCH v3 03/11] target-arm: Handle always condition codes within arm_test_cc,
Richard Henderson <=
- [Qemu-devel] [PATCH v3 02/11] target-arm: Introduce DisasCompare, Richard Henderson, 2015/09/10
- [Qemu-devel] [PATCH v3 01/11] target-arm: Share all common TCG temporaries, Richard Henderson, 2015/09/10
- [Qemu-devel] [PATCH v3 04/11] target-arm: Use setcond and movcond for csel, Richard Henderson, 2015/09/10
- [Qemu-devel] [PATCH v3 07/11] target-arm: Recognize SXTB, SXTH, SXTW, ASR, Richard Henderson, 2015/09/10
- [Qemu-devel] [PATCH v3 08/11] target-arm: Recognize UXTB, UXTH, LSR, LSL, Richard Henderson, 2015/09/10
- [Qemu-devel] [PATCH v3 05/11] target-arm: Implement ccmp branchless, Richard Henderson, 2015/09/10
- [Qemu-devel] [PATCH v3 09/11] target-arm: Eliminate unnecessary zero-extend in disas_bitfield, Richard Henderson, 2015/09/10
- [Qemu-devel] [PATCH v3 11/11] target-arm: Use tcg_gen_extrh_i64_i32, Richard Henderson, 2015/09/10
- [Qemu-devel] [PATCH v3 06/11] target-arm: Implement fcsel with movcond, Richard Henderson, 2015/09/10
- [Qemu-devel] [PATCH v3 10/11] target-arm: Recognize ROR, Richard Henderson, 2015/09/10