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[Qemu-devel] [PATCH v5 02/33] target-arm: add arm_is_secure() function
From: |
Greg Bellows |
Subject: |
[Qemu-devel] [PATCH v5 02/33] target-arm: add arm_is_secure() function |
Date: |
Tue, 30 Sep 2014 16:49:14 -0500 |
From: Fabian Aggeler <address@hidden>
arm_is_secure() function allows to determine CPU security state
if the CPU implements Security Extensions/EL3.
arm_is_secure_below_el3() returns true if CPU is in secure state
below EL3.
Signed-off-by: Sergey Fedorov <address@hidden>
Signed-off-by: Fabian Aggeler <address@hidden>
Signed-off-by: Greg Bellows <address@hidden>
---
target-arm/cpu.h | 38 ++++++++++++++++++++++++++++++++++++++
1 file changed, 38 insertions(+)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 81fffd2..10afef0 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -753,6 +753,44 @@ static inline int arm_feature(CPUARMState *env, int
feature)
return (env->features & (1ULL << feature)) != 0;
}
+
+/* Return true if exception level below EL3 is in secure state */
+static inline bool arm_is_secure_below_el3(CPUARMState *env)
+{
+#if !defined(CONFIG_USER_ONLY)
+ if (arm_feature(env, ARM_FEATURE_EL3)) {
+ return !(env->cp15.scr_el3 & SCR_NS);
+ } else if (arm_feature(env, ARM_FEATURE_EL2)) {
+ return false;
+ } else {
+ /* IMPDEF: QEMU defaults to non-secure */
+ return false;
+ }
+#else
+ return false;
+#endif
+}
+
+/* Return true if the processor is in secure state */
+static inline bool arm_is_secure(CPUARMState *env)
+{
+#if !defined(CONFIG_USER_ONLY)
+ if (arm_feature(env, ARM_FEATURE_EL3)) {
+ if (env->aarch64 && extract32(env->pstate, 2, 2) == 3) {
+ /* CPU currently in Aarch64 state and EL3 */
+ return true;
+ } else if (!env->aarch64 &&
+ (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) {
+ /* CPU currently in Aarch32 state and monitor mode */
+ return true;
+ }
+ }
+ return arm_is_secure_below_el3(env);
+#else
+ return false;
+#endif
+}
+
/* Return true if the specified exception level is running in AArch64 state. */
static inline bool arm_el_is_aa64(CPUARMState *env, int el)
{
--
1.8.3.2
- [Qemu-devel] [PATCH v5 00/33] target-arm: add Security Extensions for CPUs, Greg Bellows, 2014/09/30
- [Qemu-devel] [PATCH v5 03/33] target-arm: reject switching to monitor mode, Greg Bellows, 2014/09/30
- [Qemu-devel] [PATCH v5 05/33] target-arm: make arm_current_pl() return PL3, Greg Bellows, 2014/09/30
- [Qemu-devel] [PATCH v5 01/33] target-arm: increase arrays of registers R13 & R14, Greg Bellows, 2014/09/30
- [Qemu-devel] [PATCH v5 04/33] target-arm: rename arm_current_pl to arm_current_el, Greg Bellows, 2014/09/30
- [Qemu-devel] [PATCH v5 02/33] target-arm: add arm_is_secure() function,
Greg Bellows <=
- [Qemu-devel] [PATCH v5 07/33] target-arm: extend async excp masking, Greg Bellows, 2014/09/30
- [Qemu-devel] [PATCH v5 08/33] target-arm: add async excp target_el function, Greg Bellows, 2014/09/30
- [Qemu-devel] [PATCH v5 10/33] target-arm: add non-secure Translation Block flag, Greg Bellows, 2014/09/30
- [Qemu-devel] [PATCH v5 06/33] target-arm: A32: Emulate the SMC instruction, Greg Bellows, 2014/09/30
- [Qemu-devel] [PATCH v5 11/33] target-arm: arrayfying fieldoffset for banking, Greg Bellows, 2014/09/30
- [Qemu-devel] [PATCH v5 09/33] target-arm: add macros to access banked registers, Greg Bellows, 2014/09/30
- [Qemu-devel] [PATCH v5 12/33] target-arm: insert Aarch32 cpregs twice into hashtable, Greg Bellows, 2014/09/30
- [Qemu-devel] [PATCH v5 13/33] target-arm: move Aarch32 SCR into security reglist, Greg Bellows, 2014/09/30
- [Qemu-devel] [PATCH v5 14/33] target-arm: implement IRQ/FIQ routing to Monitor mode, Greg Bellows, 2014/09/30