[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PATCH v5 05/33] target-arm: make arm_current_pl() return P
From: |
Greg Bellows |
Subject: |
[Qemu-devel] [PATCH v5 05/33] target-arm: make arm_current_pl() return PL3 |
Date: |
Tue, 30 Sep 2014 16:49:17 -0500 |
From: Fabian Aggeler <address@hidden>
Make arm_current_pl() return PL3 for secure PL1 and monitor mode.
Increase MMU modes since mmu_index is directly infered from arm_
current_pl(). Changes assertion in arm_el_is_aa64() to allow EL3.
Signed-off-by: Fabian Aggeler <address@hidden>
Signed-off-by: Greg Bellows <address@hidden>
---
target-arm/cpu.h | 15 +++++++++------
1 file changed, 9 insertions(+), 6 deletions(-)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 101d139..c000716 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -100,7 +100,7 @@ typedef uint32_t ARMReadCPFunc(void *opaque, int cp_info,
struct arm_boot_info;
-#define NB_MMU_MODES 2
+#define NB_MMU_MODES 4
/* We currently assume float and double are IEEE single and double
precision respectively.
@@ -753,7 +753,6 @@ static inline int arm_feature(CPUARMState *env, int feature)
return (env->features & (1ULL << feature)) != 0;
}
-
/* Return true if exception level below EL3 is in secure state */
static inline bool arm_is_secure_below_el3(CPUARMState *env)
{
@@ -794,11 +793,12 @@ static inline bool arm_is_secure(CPUARMState *env)
/* Return true if the specified exception level is running in AArch64 state. */
static inline bool arm_el_is_aa64(CPUARMState *env, int el)
{
- /* We don't currently support EL2 or EL3, and this isn't valid for EL0
+ /* We don't currently support EL2, and this isn't valid for EL0
* (if we're in EL0, is_a64() is what you want, and if we're not in EL0
* then the state of EL0 isn't well defined.)
*/
- assert(el == 1);
+ assert(el == 1 || el == 3);
+
/* AArch64-capable CPUs always run with EL1 in AArch64 mode. This
* is a QEMU-imposed simplification which we may wish to change later.
* If we in future support EL2 and/or EL3, then the state of lower
@@ -990,9 +990,12 @@ static inline int arm_current_el(CPUARMState *env)
if ((env->uncached_cpsr & 0x1f) == ARM_CPU_MODE_USR) {
return 0;
+ } else if (arm_is_secure(env)) {
+ /* Secure PL1 and monitor mode are mapped to PL3 */
+ return 3;
}
- /* We don't currently implement the Virtualization or TrustZone
- * extensions, so PL2 and PL3 don't exist for us.
+ /* We currently do not implement the Virtualization extensions, so PL2 does
+ * not exist for us.
*/
return 1;
}
--
1.8.3.2
- [Qemu-devel] [PATCH v5 00/33] target-arm: add Security Extensions for CPUs, Greg Bellows, 2014/09/30
- [Qemu-devel] [PATCH v5 03/33] target-arm: reject switching to monitor mode, Greg Bellows, 2014/09/30
- [Qemu-devel] [PATCH v5 05/33] target-arm: make arm_current_pl() return PL3,
Greg Bellows <=
- [Qemu-devel] [PATCH v5 01/33] target-arm: increase arrays of registers R13 & R14, Greg Bellows, 2014/09/30
- [Qemu-devel] [PATCH v5 04/33] target-arm: rename arm_current_pl to arm_current_el, Greg Bellows, 2014/09/30
- [Qemu-devel] [PATCH v5 02/33] target-arm: add arm_is_secure() function, Greg Bellows, 2014/09/30
- [Qemu-devel] [PATCH v5 07/33] target-arm: extend async excp masking, Greg Bellows, 2014/09/30
- [Qemu-devel] [PATCH v5 08/33] target-arm: add async excp target_el function, Greg Bellows, 2014/09/30
- [Qemu-devel] [PATCH v5 10/33] target-arm: add non-secure Translation Block flag, Greg Bellows, 2014/09/30
- [Qemu-devel] [PATCH v5 06/33] target-arm: A32: Emulate the SMC instruction, Greg Bellows, 2014/09/30