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[Qemu-devel] [PATCH v5 14/33] target-arm: implement IRQ/FIQ routing to M
From: |
Greg Bellows |
Subject: |
[Qemu-devel] [PATCH v5 14/33] target-arm: implement IRQ/FIQ routing to Monitor mode |
Date: |
Tue, 30 Sep 2014 16:49:26 -0500 |
From: Fabian Aggeler <address@hidden>
SCR.{IRQ/FIQ} bits allow to route IRQ/FIQ exceptions to monitor CPU
mode. When taking IRQ exception to monitor mode FIQ exception is
additionally masked.
Signed-off-by: Sergey Fedorov <address@hidden>
Signed-off-by: Fabian Aggeler <address@hidden>
Signed-off-by: Greg Bellows <address@hidden>
---
target-arm/helper.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index cb2eb3c..8cc94ce 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -4213,12 +4213,21 @@ void arm_cpu_do_interrupt(CPUState *cs)
/* Disable IRQ and imprecise data aborts. */
mask = CPSR_A | CPSR_I;
offset = 4;
+ if (env->cp15.scr_el3 & SCR_IRQ) {
+ /* IRQ routed to monitor mode */
+ new_mode = ARM_CPU_MODE_MON;
+ mask |= CPSR_F;
+ }
break;
case EXCP_FIQ:
new_mode = ARM_CPU_MODE_FIQ;
addr = 0x1c;
/* Disable FIQ, IRQ and imprecise data aborts. */
mask = CPSR_A | CPSR_I | CPSR_F;
+ if (env->cp15.scr_el3 & SCR_FIQ) {
+ /* FIQ routed to monitor mode */
+ new_mode = ARM_CPU_MODE_MON;
+ }
offset = 4;
break;
case EXCP_SMC:
--
1.8.3.2
- [Qemu-devel] [PATCH v5 04/33] target-arm: rename arm_current_pl to arm_current_el, (continued)
- [Qemu-devel] [PATCH v5 04/33] target-arm: rename arm_current_pl to arm_current_el, Greg Bellows, 2014/09/30
- [Qemu-devel] [PATCH v5 02/33] target-arm: add arm_is_secure() function, Greg Bellows, 2014/09/30
- [Qemu-devel] [PATCH v5 07/33] target-arm: extend async excp masking, Greg Bellows, 2014/09/30
- [Qemu-devel] [PATCH v5 08/33] target-arm: add async excp target_el function, Greg Bellows, 2014/09/30
- [Qemu-devel] [PATCH v5 10/33] target-arm: add non-secure Translation Block flag, Greg Bellows, 2014/09/30
- [Qemu-devel] [PATCH v5 06/33] target-arm: A32: Emulate the SMC instruction, Greg Bellows, 2014/09/30
- [Qemu-devel] [PATCH v5 11/33] target-arm: arrayfying fieldoffset for banking, Greg Bellows, 2014/09/30
- [Qemu-devel] [PATCH v5 09/33] target-arm: add macros to access banked registers, Greg Bellows, 2014/09/30
- [Qemu-devel] [PATCH v5 12/33] target-arm: insert Aarch32 cpregs twice into hashtable, Greg Bellows, 2014/09/30
- [Qemu-devel] [PATCH v5 13/33] target-arm: move Aarch32 SCR into security reglist, Greg Bellows, 2014/09/30
- [Qemu-devel] [PATCH v5 14/33] target-arm: implement IRQ/FIQ routing to Monitor mode,
Greg Bellows <=
- [Qemu-devel] [PATCH v5 16/33] target-arm: add NSACR register, Greg Bellows, 2014/09/30
- [Qemu-devel] [PATCH v5 17/33] target-arm: add SDER definition, Greg Bellows, 2014/09/30
- [Qemu-devel] [PATCH v5 15/33] target-arm: Respect SCR.FW, SCR.AW and SCTLR.NMFI, Greg Bellows, 2014/09/30
- [Qemu-devel] [PATCH v5 20/33] target-arm: make CSSELR banked, Greg Bellows, 2014/09/30
- [Qemu-devel] [PATCH v5 19/33] target-arm: add SCTLR_EL3 and make SCTLR banked, Greg Bellows, 2014/09/30
- [Qemu-devel] [PATCH v5 18/33] target-arm: add MVBAR support, Greg Bellows, 2014/09/30
- [Qemu-devel] [PATCH v5 21/33] target-arm: add TTBR0_EL3 and make TTBR0/1 banked, Greg Bellows, 2014/09/30
- [Qemu-devel] [PATCH v5 24/33] target-arm: make DACR banked, Greg Bellows, 2014/09/30
- [Qemu-devel] [PATCH v5 23/33] target-arm: make c2_mask and c2_base_mask banked, Greg Bellows, 2014/09/30
- [Qemu-devel] [PATCH v5 27/33] target-arm: make IFAR/DFAR banked, Greg Bellows, 2014/09/30