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Re: [Qemu-devel] [PATCH v5 34/37] target-arm: Implement CBAR for Cortex-
From: |
Peter Maydell |
Subject: |
Re: [Qemu-devel] [PATCH v5 34/37] target-arm: Implement CBAR for Cortex-A57 |
Date: |
Fri, 4 Apr 2014 14:05:16 +0100 |
On 4 April 2014 13:32, Peter Crosthwaite <address@hidden> wrote:
> On Fri, Apr 4, 2014 at 6:25 PM, Peter Maydell <address@hidden> wrote:
>> On 4 April 2014 06:32, Peter Crosthwaite <address@hidden> wrote:
>>>> + if (arm_feature(env, ARM_FEATURE_AARCH64)) {
>>>> + /* 32 bit view is [31:18] 0...0 [43:32]. */
>>>> + uint32_t cbar32 = cpu->reset_cbar
>>>
>>> Should you extract64 on the lower order bits as well to avoid weird |
>>> results on a misaligned reset_cbar (or perhaps its worth an assert?).
>>
>> Can't assert, it's a QOM property; we could perhaps validate
>> earlier on in init,
>
> Is realize allowed to fail due to bad property values?
Yes; see for instance hw/intc/arm_gic_common.c : realize
gets an Error** so it can fail nicely in this situation.
> Thinking more
> about it, perhaps the ideal solution is to populate the Error **
> passed to realize and bail out and let the realize() caller deal with
> it.
Yep...
> but that might be a bit painful to find a suitable
>> place to put it. extracting the low bits too seems a reasonable
>> compromise.
...but as I say it doesn't really seem worth messing about
plumbing the Error** into the right places for this corner
case.
thanks
-- PMM