[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [Qemu-devel] [PATCH v5 35/37] target-arm: Make Cortex-A15 CBAR read-
From: |
Peter Crosthwaite |
Subject: |
Re: [Qemu-devel] [PATCH v5 35/37] target-arm: Make Cortex-A15 CBAR read-only |
Date: |
Fri, 4 Apr 2014 15:33:31 +1000 |
On Sat, Mar 29, 2014 at 2:10 AM, Peter Maydell <address@hidden> wrote:
> The Cortex-A15's CBAR register is actually read-only (unlike that
> of the Cortex-A9). Correct our model to match the hardware.
>
> Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>
> ---
> target-arm/cpu.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target-arm/cpu.c b/target-arm/cpu.c
> index f9f6187..c0ddc3e 100644
> --- a/target-arm/cpu.c
> +++ b/target-arm/cpu.c
> @@ -744,7 +744,7 @@ static void cortex_a15_initfn(Object *obj)
> set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
> set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
> set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
> - set_feature(&cpu->env, ARM_FEATURE_CBAR);
> + set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
> set_feature(&cpu->env, ARM_FEATURE_LPAE);
> cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15;
> cpu->midr = 0x412fc0f1;
> --
> 1.9.0
>
>
[Prev in Thread] |
Current Thread |
[Next in Thread] |
- Re: [Qemu-devel] [PATCH v5 35/37] target-arm: Make Cortex-A15 CBAR read-only,
Peter Crosthwaite <=