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[Qemu-devel] [PULL 35/37] target-arm: Implement ARMv8 SIMD VMAXNM and VM
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 35/37] target-arm: Implement ARMv8 SIMD VMAXNM and VMINNM instructions. |
Date: |
Tue, 10 Dec 2013 14:43:31 +0000 |
From: Will Newton <address@hidden>
This adds support for the ARMv8 Advanced SIMD VMAXNM and VMINNM
instructions.
Signed-off-by: Will Newton <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
target-arm/translate.c | 31 ++++++++++++++++++++++---------
1 file changed, 22 insertions(+), 9 deletions(-)
diff --git a/target-arm/translate.c b/target-arm/translate.c
index 9a8069e..73ed266 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -4553,7 +4553,7 @@ static void gen_neon_narrow_op(int op, int u, int size,
#define NEON_3R_FLOAT_CMP 28 /* float VCEQ, VCGE, VCGT */
#define NEON_3R_FLOAT_ACMP 29 /* float VACGE, VACGT, VACLE, VACLT */
#define NEON_3R_FLOAT_MINMAX 30 /* float VMIN, VMAX */
-#define NEON_3R_VRECPS_VRSQRTS 31 /* float VRECPS, VRSQRTS */
+#define NEON_3R_FLOAT_MISC 31 /* float VRECPS, VRSQRTS, VMAXNM/MINNM */
static const uint8_t neon_3r_sizes[] = {
[NEON_3R_VHADD] = 0x7,
@@ -4586,7 +4586,7 @@ static const uint8_t neon_3r_sizes[] = {
[NEON_3R_FLOAT_CMP] = 0x5, /* size bit 1 encodes op */
[NEON_3R_FLOAT_ACMP] = 0x5, /* size bit 1 encodes op */
[NEON_3R_FLOAT_MINMAX] = 0x5, /* size bit 1 encodes op */
- [NEON_3R_VRECPS_VRSQRTS] = 0x5, /* size bit 1 encodes op */
+ [NEON_3R_FLOAT_MISC] = 0x5, /* size bit 1 encodes op */
};
/* Symbolic constants for op fields for Neon 2-register miscellaneous.
@@ -4847,8 +4847,9 @@ static int disas_neon_data_insn(CPUARMState * env,
DisasContext *s, uint32_t ins
return 1;
}
break;
- case NEON_3R_VRECPS_VRSQRTS:
- if (u) {
+ case NEON_3R_FLOAT_MISC:
+ /* VMAXNM/VMINNM in ARMv8 */
+ if (u && !arm_feature(env, ARM_FEATURE_V8)) {
return 1;
}
break;
@@ -5137,11 +5138,23 @@ static int disas_neon_data_insn(CPUARMState * env,
DisasContext *s, uint32_t ins
tcg_temp_free_ptr(fpstatus);
break;
}
- case NEON_3R_VRECPS_VRSQRTS:
- if (size == 0)
- gen_helper_recps_f32(tmp, tmp, tmp2, cpu_env);
- else
- gen_helper_rsqrts_f32(tmp, tmp, tmp2, cpu_env);
+ case NEON_3R_FLOAT_MISC:
+ if (u) {
+ /* VMAXNM/VMINNM */
+ TCGv_ptr fpstatus = get_fpstatus_ptr(1);
+ if (size == 0) {
+ gen_helper_vfp_maxnms(tmp, tmp, tmp2, fpstatus);
+ } else {
+ gen_helper_vfp_minnms(tmp, tmp, tmp2, fpstatus);
+ }
+ tcg_temp_free_ptr(fpstatus);
+ } else {
+ if (size == 0) {
+ gen_helper_recps_f32(tmp, tmp, tmp2, cpu_env);
+ } else {
+ gen_helper_rsqrts_f32(tmp, tmp, tmp2, cpu_env);
+ }
+ }
break;
case NEON_3R_VFM:
{
--
1.8.5
- [Qemu-devel] [PULL 24/37] net/cadence_gem: Add missing VMSTATE_END_OF_LIST, (continued)
- [Qemu-devel] [PULL 24/37] net/cadence_gem: Add missing VMSTATE_END_OF_LIST, Peter Maydell, 2013/12/10
- [Qemu-devel] [PULL 10/37] target-arm: Add ARMCPU field for Linux device-tree 'compatible' string, Peter Maydell, 2013/12/10
- [Qemu-devel] [PULL 28/37] net/cadence_gem: Improve can_receive debug printfery, Peter Maydell, 2013/12/10
- [Qemu-devel] [PULL 29/37] net/cadence_gem: Don't rx packets when no rx buffer available, Peter Maydell, 2013/12/10
- [Qemu-devel] [PULL 26/37] net/cadence_gem: Fix small packet FCS stripping, Peter Maydell, 2013/12/10
- [Qemu-devel] [PULL 09/37] target-arm: Provide PSCI constants to generic QEMU code, Peter Maydell, 2013/12/10
- [Qemu-devel] [PULL 27/37] net/cadence_gem: Fix register w1c logic, Peter Maydell, 2013/12/10
- [Qemu-devel] [PULL 11/37] target-arm: Allow secondary KVM CPUs to be booted via PSCI, Peter Maydell, 2013/12/10
- [Qemu-devel] [PULL 03/37] cpu/a9mpcore: reorder operations/declarations, Peter Maydell, 2013/12/10
- [Qemu-devel] [PULL 22/37] net/cadence_gem: Implement SAR match bit in rx desc, Peter Maydell, 2013/12/10
- [Qemu-devel] [PULL 35/37] target-arm: Implement ARMv8 SIMD VMAXNM and VMINNM instructions.,
Peter Maydell <=
- [Qemu-devel] [PULL 25/37] net/cadence_gem: Fix rx multi-fragment packets, Peter Maydell, 2013/12/10
- [Qemu-devel] [PULL 19/37] net/cadence_gem: simplify rx buf descriptor walking, Peter Maydell, 2013/12/10
- [Qemu-devel] [PULL 15/37] hw/arm/virt: Support -cpu host, Peter Maydell, 2013/12/10
- [Qemu-devel] [PULL 06/37] target-arm: Provide mechanism for getting KVM constants even if not CONFIG_KVM, Peter Maydell, 2013/12/10
- [Qemu-devel] [PULL 12/37] hw/arm: Add 'virt' platform, Peter Maydell, 2013/12/10
- [Qemu-devel] [PULL 30/37] target-arm: Move call to disas_vfp_insn out of disas_coproc_insn., Peter Maydell, 2013/12/10
- [Qemu-devel] [PULL 07/37] device_tree.c: Terminate the empty reservemap in create_device_tree(), Peter Maydell, 2013/12/10
- [Qemu-devel] [PULL 04/37] hw/timer: Introduce ARM A9 Global Timer., Peter Maydell, 2013/12/10
- [Qemu-devel] [PULL 20/37] net/cadence_gem: Prefetch rx descriptors ASAP, Peter Maydell, 2013/12/10
- [Qemu-devel] [PULL 01/37] integrator/cp: add support for REFCNT register, Peter Maydell, 2013/12/10