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[Qemu-devel] [PULL 01/37] integrator/cp: add support for REFCNT register
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 01/37] integrator/cp: add support for REFCNT register |
Date: |
Tue, 10 Dec 2013 14:42:57 +0000 |
From: Jan Petrous <address@hidden>
Linux kernel from version 3.4 requires CM_REFCNT register for sched timer
for Integrator/CP board (integrator_defconfig).
See http://infocenter.arm.com/help/topic/com.arm.doc.dui0138e/ch04s06s11.html
Signed-off-by: Jan Petrous <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
---
hw/arm/integratorcp.c | 13 ++++++++++---
1 file changed, 10 insertions(+), 3 deletions(-)
diff --git a/hw/arm/integratorcp.c b/hw/arm/integratorcp.c
index c44b2a4..a759689 100644
--- a/hw/arm/integratorcp.c
+++ b/hw/arm/integratorcp.c
@@ -36,6 +36,7 @@ typedef struct IntegratorCMState {
uint32_t cm_init;
uint32_t cm_flags;
uint32_t cm_nvflags;
+ uint32_t cm_refcnt_offset;
uint32_t int_level;
uint32_t irq_enabled;
uint32_t fiq_enabled;
@@ -82,9 +83,13 @@ static uint64_t integratorcm_read(void *opaque, hwaddr
offset,
return s->cm_sdram;
case 9: /* CM_INIT */
return s->cm_init;
- case 10: /* CM_REFCT */
- /* ??? High frequency timer. */
- hw_error("integratorcm_read: CM_REFCT");
+ case 10: /* CM_REFCNT */
+ /* This register, CM_REFCNT, provides a 32-bit count value.
+ * The count increments at the fixed reference clock frequency of 24MHz
+ * and can be used as a real-time counter.
+ */
+ return (uint32_t)muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 24,
+ 1000) - s->cm_refcnt_offset;
case 12: /* CM_FLAGS */
return s->cm_flags;
case 14: /* CM_NVFLAGS */
@@ -257,6 +262,8 @@ static int integratorcm_init(SysBusDevice *dev)
}
memcpy(integrator_spd + 73, "QEMU-MEMORY", 11);
s->cm_init = 0x00000112;
+ s->cm_refcnt_offset = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 24,
+ 1000);
memory_region_init_ram(&s->flash, OBJECT(s), "integrator.flash", 0x100000);
vmstate_register_ram_global(&s->flash);
--
1.8.5
- [Qemu-devel] [PULL 35/37] target-arm: Implement ARMv8 SIMD VMAXNM and VMINNM instructions., (continued)
- [Qemu-devel] [PULL 35/37] target-arm: Implement ARMv8 SIMD VMAXNM and VMINNM instructions., Peter Maydell, 2013/12/10
- [Qemu-devel] [PULL 25/37] net/cadence_gem: Fix rx multi-fragment packets, Peter Maydell, 2013/12/10
- [Qemu-devel] [PULL 19/37] net/cadence_gem: simplify rx buf descriptor walking, Peter Maydell, 2013/12/10
- [Qemu-devel] [PULL 15/37] hw/arm/virt: Support -cpu host, Peter Maydell, 2013/12/10
- [Qemu-devel] [PULL 06/37] target-arm: Provide mechanism for getting KVM constants even if not CONFIG_KVM, Peter Maydell, 2013/12/10
- [Qemu-devel] [PULL 12/37] hw/arm: Add 'virt' platform, Peter Maydell, 2013/12/10
- [Qemu-devel] [PULL 30/37] target-arm: Move call to disas_vfp_insn out of disas_coproc_insn., Peter Maydell, 2013/12/10
- [Qemu-devel] [PULL 07/37] device_tree.c: Terminate the empty reservemap in create_device_tree(), Peter Maydell, 2013/12/10
- [Qemu-devel] [PULL 04/37] hw/timer: Introduce ARM A9 Global Timer., Peter Maydell, 2013/12/10
- [Qemu-devel] [PULL 20/37] net/cadence_gem: Prefetch rx descriptors ASAP, Peter Maydell, 2013/12/10
- [Qemu-devel] [PULL 01/37] integrator/cp: add support for REFCNT register,
Peter Maydell <=
- [Qemu-devel] [PULL 05/37] cpu/a9mpcore: Add Global Timer, Peter Maydell, 2013/12/10
- [Qemu-devel] [PULL 08/37] hw/arm/boot: Allow boards to provide an fdt blob, Peter Maydell, 2013/12/10
- [Qemu-devel] [PULL 23/37] net/cadence_gem: Implement SAR (de)activation, Peter Maydell, 2013/12/10
- [Qemu-devel] [PULL 14/37] target-arm: Provide '-cpu host' when running KVM, Peter Maydell, 2013/12/10
- [Qemu-devel] [PULL 13/37] target-arm: Don't hardcode KVM target CPU to be A15, Peter Maydell, 2013/12/10
- [Qemu-devel] [PULL 21/37] net/cadence_gem: Implement RX descriptor match mode flags, Peter Maydell, 2013/12/10
- [Qemu-devel] [PULL 37/37] target-arm: fix TTBCR write masking, Peter Maydell, 2013/12/10
- [Qemu-devel] [PULL 18/37] net/cadence_gem: Don't assert against 0 buffer address, Peter Maydell, 2013/12/10