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[Qemu-devel] [PULL 03/37] cpu/a9mpcore: reorder operations/declarations
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 03/37] cpu/a9mpcore: reorder operations/declarations |
Date: |
Tue, 10 Dec 2013 14:42:59 +0000 |
From: Peter Crosthwaite <address@hidden>
To make it consistent for easier code reading. The order in which
variables are defined and functions are called is set to match the
address map ordering.
The new consistent order of doing stuff is:
SCU -> GIC -> MPTimer -> WDT.
0 functional change.
Signed-off-by: Peter Crosthwaite <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
hw/cpu/a9mpcore.c | 28 ++++++++++++++--------------
include/hw/cpu/a9mpcore.h | 2 +-
2 files changed, 15 insertions(+), 15 deletions(-)
diff --git a/hw/cpu/a9mpcore.c b/hw/cpu/a9mpcore.c
index 1123101..a38464b 100644
--- a/hw/cpu/a9mpcore.c
+++ b/hw/cpu/a9mpcore.c
@@ -24,12 +24,12 @@ static void a9mp_priv_initfn(Object *obj)
memory_region_init(&s->container, obj, "a9mp-priv-container", 0x2000);
sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->container);
- object_initialize(&s->gic, sizeof(s->gic), TYPE_ARM_GIC);
- qdev_set_parent_bus(DEVICE(&s->gic), sysbus_get_default());
-
object_initialize(&s->scu, sizeof(s->scu), TYPE_A9_SCU);
qdev_set_parent_bus(DEVICE(&s->scu), sysbus_get_default());
+ object_initialize(&s->gic, sizeof(s->gic), TYPE_ARM_GIC);
+ qdev_set_parent_bus(DEVICE(&s->gic), sysbus_get_default());
+
object_initialize(&s->mptimer, sizeof(s->mptimer), TYPE_ARM_MPTIMER);
qdev_set_parent_bus(DEVICE(&s->mptimer), sysbus_get_default());
@@ -41,11 +41,20 @@ static void a9mp_priv_realize(DeviceState *dev, Error
**errp)
{
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
A9MPPrivState *s = A9MPCORE_PRIV(dev);
- DeviceState *gicdev, *scudev, *mptimerdev, *wdtdev;
- SysBusDevice *mptimerbusdev, *wdtbusdev, *gicbusdev, *scubusdev;
+ DeviceState *scudev, *gicdev, *mptimerdev, *wdtdev;
+ SysBusDevice *scubusdev, *gicbusdev, *mptimerbusdev, *wdtbusdev;
Error *err = NULL;
int i;
+ scudev = DEVICE(&s->scu);
+ qdev_prop_set_uint32(scudev, "num-cpu", s->num_cpu);
+ object_property_set_bool(OBJECT(&s->scu), true, "realized", &err);
+ if (err != NULL) {
+ error_propagate(errp, err);
+ return;
+ }
+ scubusdev = SYS_BUS_DEVICE(&s->scu);
+
gicdev = DEVICE(&s->gic);
qdev_prop_set_uint32(gicdev, "num-cpu", s->num_cpu);
qdev_prop_set_uint32(gicdev, "num-irq", s->num_irq);
@@ -62,15 +71,6 @@ static void a9mp_priv_realize(DeviceState *dev, Error **errp)
/* Pass through inbound GPIO lines to the GIC */
qdev_init_gpio_in(dev, a9mp_priv_set_irq, s->num_irq - 32);
- scudev = DEVICE(&s->scu);
- qdev_prop_set_uint32(scudev, "num-cpu", s->num_cpu);
- object_property_set_bool(OBJECT(&s->scu), true, "realized", &err);
- if (err != NULL) {
- error_propagate(errp, err);
- return;
- }
- scubusdev = SYS_BUS_DEVICE(&s->scu);
-
mptimerdev = DEVICE(&s->mptimer);
qdev_prop_set_uint32(mptimerdev, "num-cpu", s->num_cpu);
object_property_set_bool(OBJECT(&s->mptimer), true, "realized", &err);
diff --git a/include/hw/cpu/a9mpcore.h b/include/hw/cpu/a9mpcore.h
index 010489b..8eece07 100644
--- a/include/hw/cpu/a9mpcore.h
+++ b/include/hw/cpu/a9mpcore.h
@@ -28,8 +28,8 @@ typedef struct A9MPPrivState {
MemoryRegion container;
uint32_t num_irq;
- GICState gic;
A9SCUState scu;
+ GICState gic;
ARMMPTimerState mptimer;
ARMMPTimerState wdt;
} A9MPPrivState;
--
1.8.5
- [Qemu-devel] [PULL 32/37] softfloat: Remove unused argument from MINMAX macro., (continued)
- [Qemu-devel] [PULL 32/37] softfloat: Remove unused argument from MINMAX macro., Peter Maydell, 2013/12/10
- [Qemu-devel] [PULL 31/37] target-arm: Implement ARMv8 VSEL instruction., Peter Maydell, 2013/12/10
- [Qemu-devel] [PULL 24/37] net/cadence_gem: Add missing VMSTATE_END_OF_LIST, Peter Maydell, 2013/12/10
- [Qemu-devel] [PULL 10/37] target-arm: Add ARMCPU field for Linux device-tree 'compatible' string, Peter Maydell, 2013/12/10
- [Qemu-devel] [PULL 28/37] net/cadence_gem: Improve can_receive debug printfery, Peter Maydell, 2013/12/10
- [Qemu-devel] [PULL 29/37] net/cadence_gem: Don't rx packets when no rx buffer available, Peter Maydell, 2013/12/10
- [Qemu-devel] [PULL 26/37] net/cadence_gem: Fix small packet FCS stripping, Peter Maydell, 2013/12/10
- [Qemu-devel] [PULL 09/37] target-arm: Provide PSCI constants to generic QEMU code, Peter Maydell, 2013/12/10
- [Qemu-devel] [PULL 27/37] net/cadence_gem: Fix register w1c logic, Peter Maydell, 2013/12/10
- [Qemu-devel] [PULL 11/37] target-arm: Allow secondary KVM CPUs to be booted via PSCI, Peter Maydell, 2013/12/10
- [Qemu-devel] [PULL 03/37] cpu/a9mpcore: reorder operations/declarations,
Peter Maydell <=
- [Qemu-devel] [PULL 22/37] net/cadence_gem: Implement SAR match bit in rx desc, Peter Maydell, 2013/12/10
- [Qemu-devel] [PULL 35/37] target-arm: Implement ARMv8 SIMD VMAXNM and VMINNM instructions., Peter Maydell, 2013/12/10
- [Qemu-devel] [PULL 25/37] net/cadence_gem: Fix rx multi-fragment packets, Peter Maydell, 2013/12/10
- [Qemu-devel] [PULL 19/37] net/cadence_gem: simplify rx buf descriptor walking, Peter Maydell, 2013/12/10
- [Qemu-devel] [PULL 15/37] hw/arm/virt: Support -cpu host, Peter Maydell, 2013/12/10
- [Qemu-devel] [PULL 06/37] target-arm: Provide mechanism for getting KVM constants even if not CONFIG_KVM, Peter Maydell, 2013/12/10
- [Qemu-devel] [PULL 12/37] hw/arm: Add 'virt' platform, Peter Maydell, 2013/12/10
- [Qemu-devel] [PULL 30/37] target-arm: Move call to disas_vfp_insn out of disas_coproc_insn., Peter Maydell, 2013/12/10
- [Qemu-devel] [PULL 07/37] device_tree.c: Terminate the empty reservemap in create_device_tree(), Peter Maydell, 2013/12/10
- [Qemu-devel] [PULL 04/37] hw/timer: Introduce ARM A9 Global Timer., Peter Maydell, 2013/12/10