commit-gnuradio
[Top][All Lists]
Advanced

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

[Commit-gnuradio] r7308 - usrp2/trunk/fpga/control_lib


From: matt
Subject: [Commit-gnuradio] r7308 - usrp2/trunk/fpga/control_lib
Date: Sun, 30 Dec 2007 16:54:41 -0700 (MST)

Author: matt
Date: 2007-12-30 16:54:40 -0700 (Sun, 30 Dec 2007)
New Revision: 7308

Modified:
   usrp2/trunk/fpga/control_lib/extram_interface.v
Log:
clean up some warnings


Modified: usrp2/trunk/fpga/control_lib/extram_interface.v
===================================================================
--- usrp2/trunk/fpga/control_lib/extram_interface.v     2007-12-30 08:03:55 UTC 
(rev 7307)
+++ usrp2/trunk/fpga/control_lib/extram_interface.v     2007-12-30 23:54:40 UTC 
(rev 7308)
@@ -1,4 +1,7 @@
 
+// Temporary buffer pool storage, mostly useful for pre-generated data streams 
or
+//   for making more space to juggle packets in case of eth frames coming out 
of order
+
 module extram_interface
   (input clk, input rst,
    input set_stb, input [7:0] set_addr, input [31:0] set_data,
@@ -19,8 +22,32 @@
    output RAM_OEn,
    output RAM_LDn );
 
+   // Command format --
+   //    Read/_Write , start address[17:0]
+   wire [18:0] cmd_in;
+   wire        cmd_stb, store_wr_cmd, store_rd_cmd, read_wr_cmd, read_rd_cmd;
+   wire        empty_wr_cmd, empty_rd_cmd, full_wr_cmd, full_rd_cmd;
+   
    // Dummy logic
-
    assign RAM_OEn = 1;
    
+   setting_reg #(.my_addr(0)) 
+     sr_ram_cmd (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+                .in(set_data),.out(cmd_in),.changed(cmd_stb));
+   
+   reg           cmd_stb_d1;
+   always @(posedge clk) cmd_stb_d1 <= cmd_stb;
+   assign store_wr_cmd = ~cmd_in[18] & cmd_stb & ~cmd_stb_d1;
+   assign store_rd_cmd = cmd_in[18] & cmd_stb & ~cmd_stb_d1;   
+
+   shortfifo #(.WIDTH(19)) wr_cmd_fifo
+     (.clk(clk),.rst(rst),.clear(1'b0),
+      .datain(cmd_in), .write(store_wr_cmd), .full(full_wr_cmd),
+      .dataout(), .read(read_wr_cmd), .empty(empty_wr_cmd) );
+
+   shortfifo #(.WIDTH(19)) rd_cmd_fifo
+     (.clk(clk),.rst(rst),.clear(1'b0),
+      .datain(cmd_in), .write(store_rd_cmd), .full(full_rd_cmd),
+      .dataout(), .read(read_rd_cmd), .empty(empty_rd_cmd) );
+
 endmodule // extram_interface





reply via email to

[Prev in Thread] Current Thread [Next in Thread]