[Commit-gnuradio] r7309 - usrp2/trunk/fpga/timing

[matt]

Author: matt
Date: 2007-12-30 16:56:20 -0700 (Sun, 30 Dec 2007)
New Revision: 7309

Modified:
   usrp2/trunk/fpga/timing/time_receiver.v
   usrp2/trunk/fpga/timing/time_sync.v
Log:
moved some functionality around, renamed pps to tick internally, demonstrated 
working time sync


Modified: usrp2/trunk/fpga/timing/time_receiver.v
===================================================================
--- usrp2/trunk/fpga/timing/time_receiver.v     2007-12-30 23:54:40 UTC (rev 
7308)
+++ usrp2/trunk/fpga/timing/time_receiver.v     2007-12-30 23:56:20 UTC (rev 
7309)
@@ -1,8 +1,8 @@
 
 module time_receiver
   (input clk, input rst,
-   output reg [31:0] master_time,
-   output reg sync_rcvd,
+   output [31:0] master_time,
+   output sync_rcvd,
    input exp_pps_in);
 
    wire       code_err, disp_err, dispout, complete_word;
@@ -88,20 +88,7 @@
           state <= STATE_IDLE;
        endcase // case(state)
 
-   always @(posedge clk)
-     if(rst)
-       begin
-         master_time <= 0;
-         sync_rcvd <= 0;
-       end
-     else if(complete_word & (state == STATE_T3))
-       begin
-         master_time <= {clock_a, clock_b, clock_c, dataout_reg[7:0]};
-         sync_rcvd <= 1;
-       end
-     else
-       begin
-         master_time <= master_time + 1;
-         sync_rcvd <= 0;
-       end
+   assign master_time =  {clock_a, clock_b, clock_c, dataout_reg[7:0]};
+   assign sync_rcvd = (complete_word & (state == STATE_T3));
+
 endmodule // time_sender

Modified: usrp2/trunk/fpga/timing/time_sync.v
===================================================================
--- usrp2/trunk/fpga/timing/time_sync.v 2007-12-30 23:54:40 UTC (rev 7308)
+++ usrp2/trunk/fpga/timing/time_sync.v 2007-12-30 23:56:20 UTC (rev 7309)
@@ -7,24 +7,29 @@
    input sys_clk_i, output [31:0] master_time_o,
    input pps_in, input exp_pps_in, output exp_pps_out,
    output int_o );
-
-   // Generate Internal master time if we are the master
-   reg [31:0] master_time;
+   
    wire [31:0] master_time_rcvd;
-
+   reg [31:0]  master_time;
+   wire        sync_rcvd, internal_tick, pps_ext;
+   reg [31:0]  tick_time, tick_time_wb;
+   wire        tick_free_run;
+   reg                tick_int_enable, tick_source, external_sync;
+   reg [31:0]  tick_interval;
+   
+   // Generate master time
    always @(posedge sys_clk_i)
      if(rst_i)
        master_time <= 0;
+     else if(external_sync & sync_rcvd)
+       master_time <= master_time_rcvd;
      else
        master_time <= master_time + 1;
-   assign     master_time_o = master_time;
-
-   wire       send_sync, sync_rcvd;
+   assign      master_time_o = master_time;
    
    time_sender time_sender
      (.clk(sys_clk_i),.rst(rst_i),
       .master_time(master_time),
-      .send_sync(send_sync),
+      .send_sync(internal_tick),
       .exp_pps_out(exp_pps_out) );
 
    time_receiver time_receiver
@@ -33,71 +38,57 @@
       .sync_rcvd(sync_rcvd),
       .exp_pps_in(exp_pps_in) );
 
-
-   
-   reg [31:0] pps_time, pps_time_wb;
-   reg [1:0]  pps_source;
-   reg               pps_in_d1, pps_in_d2;
-   wire       pps_free_run;
-   reg               pps_int_enable;
-   reg               exp_pps_in_decoded;
-   wire       pps_ext, pps_internal;
-   
    assign     ack_o = stb_i;
 
    always @(posedge wb_clk_i)
      if(rst_i)
        begin
-         pps_source <= 0;
-         pps_int_enable <= 0;
+         tick_source <= 0;
+         tick_int_enable <= 0;
+         external_sync <= 0;
+         tick_interval <= 100000-1;  // default to 1K times per second
        end
      else if(stb_i & we_i)
-       begin
-         pps_source <= dat_i[1:0];
-         pps_int_enable <= dat_i[2];
-       end
+       if(adr_i[2])
+        tick_interval <= dat_i;
+       else
+        begin
+           tick_source <= dat_i[0];
+           tick_int_enable <= dat_i[1];
+           external_sync <= dat_i[2];
+        end
    
    always @(posedge sys_clk_i)
-     if(pps_internal)
-       pps_time <= master_time;
+     if(internal_tick)
+       tick_time <= master_time;
 
    always @(posedge wb_clk_i)
-     pps_time_wb <= pps_time;
+     tick_time_wb <= tick_time;
    
-   assign dat_o = pps_time_wb;
-   assign int_o = pps_int_enable & pps_internal;
+   assign dat_o = tick_time_wb;
 
-   assign pps_internal = 
-         (pps_source == 1) ? pps_ext :
-         (pps_source == 2) ? exp_pps_in_decoded :
-         pps_free_run;
+   assign internal_tick = (tick_source == 0) ? tick_free_run : pps_ext;
 
-   // Generate internal free-runnning PPS clock
-   localparam ONE_SECOND = 100000000-1;  // 100 million minus 1
    reg [31:0] counter;
    always @(posedge sys_clk_i)
      if(rst_i)
        counter <= 0;
-     else if(counter == ONE_SECOND)
+     else if(tick_free_run)
        counter <= 0;
      else
        counter <= counter + 1;
-   assign pps_free_run = (counter == ONE_SECOND);
+   assign     tick_free_run = (counter >= tick_interval);
    
-   // Decode Expansion PPS Input
-   reg           exp_pps_in_d1;
-   always @(posedge sys_clk_i) 
-     begin
-       exp_pps_in_d1 <= exp_pps_in;
-       exp_pps_in_decoded <= (exp_pps_in_d1 == exp_pps_in);
-     end
-   
    // Properly Latch and edge detect External PPS input
+   reg               pps_in_d1, pps_in_d2;
    always @(posedge sys_clk_i)
      begin
        pps_in_d1 <= pps_in;
        pps_in_d2 <= pps_in_d1;
      end
    assign pps_ext = pps_in_d1 & ~pps_in_d2;
+
+   // Need to register this?
+   assign int_o = tick_int_enable & internal_tick;
    
 endmodule // time_sync