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[Commit-gnuradio] r7307 - in usrp2/trunk/fpga/opencores/aemb: doc/CVS si
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From: |
matt |
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Subject: |
[Commit-gnuradio] r7307 - in usrp2/trunk/fpga/opencores/aemb: doc/CVS sim/CVS sim/verilog sim/verilog/CVS |
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Date: |
Sun, 30 Dec 2007 01:03:55 -0700 (MST) |
Author: matt
Date: 2007-12-30 01:03:55 -0700 (Sun, 30 Dec 2007)
New Revision: 7307
Modified:
usrp2/trunk/fpga/opencores/aemb/doc/CVS/Entries
usrp2/trunk/fpga/opencores/aemb/sim/CVS/Entries
usrp2/trunk/fpga/opencores/aemb/sim/verilog/CVS/Entries
usrp2/trunk/fpga/opencores/aemb/sim/verilog/aemb2.v
usrp2/trunk/fpga/opencores/aemb/sim/verilog/edk32.v
Log:
catching up with Shawn
Modified: usrp2/trunk/fpga/opencores/aemb/doc/CVS/Entries
===================================================================
--- usrp2/trunk/fpga/opencores/aemb/doc/CVS/Entries 2007-12-30 08:03:07 UTC
(rev 7306)
+++ usrp2/trunk/fpga/opencores/aemb/doc/CVS/Entries 2007-12-30 08:03:55 UTC
(rev 7307)
@@ -1,2 +1,2 @@
-/aeMB_datasheet.pdf/1.3/Sat Nov 24 05:11:12 2007/-kb/
+/aeMB_datasheet.pdf/1.3/Mon Dec 10 00:41:19 2007/-kb/
D
Modified: usrp2/trunk/fpga/opencores/aemb/sim/CVS/Entries
===================================================================
--- usrp2/trunk/fpga/opencores/aemb/sim/CVS/Entries 2007-12-30 08:03:07 UTC
(rev 7306)
+++ usrp2/trunk/fpga/opencores/aemb/sim/CVS/Entries 2007-12-30 08:03:55 UTC
(rev 7307)
@@ -1,3 +1,3 @@
D/verilog////
-/cversim/1.5/Wed Dec 12 03:12:13 2007//
-/iversim/1.5/Wed Dec 12 03:12:13 2007//
+/cversim/1.5/Wed Dec 12 20:18:00 2007//
+/iversim/1.5/Wed Dec 12 20:18:00 2007//
Modified: usrp2/trunk/fpga/opencores/aemb/sim/verilog/CVS/Entries
===================================================================
--- usrp2/trunk/fpga/opencores/aemb/sim/verilog/CVS/Entries 2007-12-30
08:03:07 UTC (rev 7306)
+++ usrp2/trunk/fpga/opencores/aemb/sim/verilog/CVS/Entries 2007-12-30
08:03:55 UTC (rev 7307)
@@ -1,3 +1,3 @@
-/aemb2.v/1.1/Tue Dec 11 00:44:31 2007//
-/edk32.v/1.11/Wed Dec 12 03:12:13 2007//
+/aemb2.v/1.3/Sun Dec 30 08:00:30 2007//
+/edk32.v/1.12/Sun Dec 30 08:00:31 2007//
D
Modified: usrp2/trunk/fpga/opencores/aemb/sim/verilog/aemb2.v
===================================================================
--- usrp2/trunk/fpga/opencores/aemb/sim/verilog/aemb2.v 2007-12-30 08:03:07 UTC
(rev 7306)
+++ usrp2/trunk/fpga/opencores/aemb/sim/verilog/aemb2.v 2007-12-30 08:03:55 UTC
(rev 7307)
@@ -1,7 +1,6 @@
-/* $Id: aemb2.v,v 1.1 2007/12/11 00:44:31 sybreon Exp $
+/* $Id: aemb2.v,v 1.3 2007/12/28 21:44:50 sybreon Exp $
**
** AEMB2 TEST BENCH
-**
** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <address@hidden>
**
** This file is part of AEMB.
@@ -20,14 +19,11 @@
** License along with AEMB. If not, see <http:**www.gnu.org/licenses/>.
*/
-`define AEMB2_SIMULATION_KERNEL
-
module aemb2 ();
parameter IWB=16;
parameter DWB=16;
- parameter TXE = 1; ///< thread execution enable
- parameter LUT = 0; ///< further speed optimisation
+ parameter TXE = 0; ///< thread execution enable
parameter MUL = 1; ///< enable hardware multiplier
parameter BSF = 1; ///< enable barrel shifter
@@ -38,30 +34,32 @@
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
- wire [6:2] cwb_adr_o; // From dut of aeMB2_edk32.v
- wire [31:0] cwb_dat_o; // From dut of aeMB2_edk32.v
- wire [3:0] cwb_sel_o; // From dut of aeMB2_edk32.v
- wire cwb_stb_o; // From dut of
aeMB2_edk32.v
- wire [1:0] cwb_tga_o; // From dut of aeMB2_edk32.v
- wire cwb_wre_o; // From dut of
aeMB2_edk32.v
- wire [DWB-1:2] dwb_adr_o; // From dut of aeMB2_edk32.v
- wire dwb_cyc_o; // From dut of
aeMB2_edk32.v
- wire [31:0] dwb_dat_o; // From dut of aeMB2_edk32.v
- wire [3:0] dwb_sel_o; // From dut of aeMB2_edk32.v
- wire dwb_stb_o; // From dut of
aeMB2_edk32.v
- wire dwb_wre_o; // From dut of
aeMB2_edk32.v
- wire [IWB-1:2] iwb_adr_o; // From dut of aeMB2_edk32.v
- wire iwb_stb_o; // From dut of
aeMB2_edk32.v
- wire iwb_wre_o; // From dut of
aeMB2_edk32.v
+ wire [6:2] cwb_adr_o; // From dut of aeMB2_sim.v
+ wire [31:0] cwb_dat_o; // From dut of aeMB2_sim.v
+ wire [3:0] cwb_sel_o; // From dut of aeMB2_sim.v
+ wire cwb_stb_o; // From dut of
aeMB2_sim.v
+ wire [1:0] cwb_tga_o; // From dut of aeMB2_sim.v
+ wire cwb_wre_o; // From dut of
aeMB2_sim.v
+ wire [DWB-1:2] dwb_adr_o; // From dut of aeMB2_sim.v
+ wire dwb_cyc_o; // From dut of
aeMB2_sim.v
+ wire [31:0] dwb_dat_o; // From dut of aeMB2_sim.v
+ wire [3:0] dwb_sel_o; // From dut of aeMB2_sim.v
+ wire dwb_stb_o; // From dut of
aeMB2_sim.v
+ wire dwb_tga_o; // From dut of
aeMB2_sim.v
+ wire dwb_wre_o; // From dut of
aeMB2_sim.v
+ wire [IWB-1:2] iwb_adr_o; // From dut of aeMB2_sim.v
+ wire iwb_stb_o; // From dut of
aeMB2_sim.v
+ wire iwb_tga_o; // From dut of
aeMB2_sim.v
+ wire iwb_wre_o; // From dut of
aeMB2_sim.v
// End of automatics
/*AUTOREGINPUT*/
// Beginning of automatic reg inputs (for undeclared instantiated-module
inputs)
- reg cwb_ack_i; // To dut of aeMB2_edk32.v
- reg dwb_ack_i; // To dut of aeMB2_edk32.v
- reg iwb_ack_i; // To dut of aeMB2_edk32.v
- reg sys_clk_i; // To dut of aeMB2_edk32.v
- reg sys_int_i; // To dut of aeMB2_edk32.v
- reg sys_rst_i; // To dut of aeMB2_edk32.v
+ reg cwb_ack_i; // To dut of aeMB2_sim.v
+ reg dwb_ack_i; // To dut of aeMB2_sim.v
+ reg iwb_ack_i; // To dut of aeMB2_sim.v
+ reg sys_clk_i; // To dut of aeMB2_sim.v
+ reg sys_int_i; // To dut of aeMB2_sim.v
+ reg sys_rst_i; // To dut of aeMB2_sim.v
// End of automatics
// INITIAL SETUP //////////////////////////////////////////////////////
@@ -98,7 +96,7 @@
reg [15:2] dadr, iadr;
wire [31:0] dwb_dat_t = ram[dwb_adr_o];
- wire [31:0] iwb_dat_i = ram[iadr];
+ wire [31:0] iwb_dat_i = rom[iadr];
wire [31:0] dwb_dat_i = ram[dadr];
wire [31:0] cwb_dat_i = cwb_adr_o;
@@ -144,6 +142,7 @@
for (i=0;i<65535;i=i+1) begin
ram[i] <= $random;
end
+ #1 $readmemh("dump.vmem",rom);
#1 $readmemh("dump.vmem",ram);
end
@@ -152,7 +151,28 @@
integer rnd;
always @(posedge sys_clk_i) begin
-
+
+ // Interrupt Monitors
+ if (!dut.sim.rMSR_IE) begin
+ rnd = $random % 30;
+ inttime = $stime + 1000 + (rnd*rnd * 10);
+ end
+ if ($stime > inttime) begin
+ sys_int_i = 1;
+ svc = 0;
+ end
+ if (($stime > inttime + 500) && !svc) begin
+ $display("\n\t*** INTERRUPT TIMEOUT ***", inttime);
+ $finish;
+ end
+ if (dwb_wre_o & (dwb_dat_o == "RTNI")) sys_int_i = 0;
+ /*
+ if (dut.regf.fRDWE && (dut.rRD == 5'h0e) && !svc && dut.gena) begin
+ svc = 1;
+ //$display("\nLATENCY: ", ($stime - inttime)/10);
+ end
+ */
+
// Pass/Fail Monitors
if (dwb_wre_o & (dwb_dat_o == "FAIL")) begin
$display("\n\tFAIL");
@@ -172,13 +192,12 @@
// INTERNAL WIRING ////////////////////////////////////////////////////
- aeMB2_edk32
+ aeMB2_sim
#(/*AUTOINSTPARAM*/
// Parameters
.IWB (IWB),
.DWB (DWB),
.TXE (TXE),
- .LUT (LUT),
.MUL (MUL),
.BSF (BSF),
.FSL (FSL),
@@ -196,9 +215,11 @@
.dwb_dat_o (dwb_dat_o[31:0]),
.dwb_sel_o (dwb_sel_o[3:0]),
.dwb_stb_o (dwb_stb_o),
+ .dwb_tga_o (dwb_tga_o),
.dwb_wre_o (dwb_wre_o),
.iwb_adr_o (iwb_adr_o[IWB-1:2]),
.iwb_stb_o (iwb_stb_o),
+ .iwb_tga_o (iwb_tga_o),
.iwb_wre_o (iwb_wre_o),
// Inputs
.cwb_ack_i (cwb_ack_i),
@@ -218,4 +239,4 @@
// Local Variables:
// verilog-library-directories:("." "../../rtl/verilog/")
// verilog-library-files:("")
-// End:
\ No newline at end of file
+// End:
Modified: usrp2/trunk/fpga/opencores/aemb/sim/verilog/edk32.v
===================================================================
--- usrp2/trunk/fpga/opencores/aemb/sim/verilog/edk32.v 2007-12-30 08:03:07 UTC
(rev 7306)
+++ usrp2/trunk/fpga/opencores/aemb/sim/verilog/edk32.v 2007-12-30 08:03:55 UTC
(rev 7307)
@@ -1,62 +1,23 @@
-// $Id: edk32.v,v 1.11 2007/12/11 00:44:31 sybreon Exp $
-//
-// AEMB EDK 3.2 Compatible Core TEST
-//
-// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <address@hidden>
-//
-// This file is part of AEMB.
-//
-// AEMB is free software: you can redistribute it and/or modify it
-// under the terms of the GNU Lesser General Public License as
-// published by the Free Software Foundation, either version 3 of the
-// License, or (at your option) any later version.
-//
-// AEMB is distributed in the hope that it will be useful, but WITHOUT
-// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
-// or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General
-// Public License for more details.
-//
-// You should have received a copy of the GNU Lesser General Public
-// License along with AEMB. If not, see <http://www.gnu.org/licenses/>.
-//
-// $Log: edk32.v,v $
-// Revision 1.11 2007/12/11 00:44:31 sybreon
-// Modified for AEMB2
-//
-// Revision 1.10 2007/11/30 17:08:30 sybreon
-// Moved simulation kernel into code.
-//
-// Revision 1.9 2007/11/20 18:36:00 sybreon
-// Removed unnecessary byte acrobatics with VMEM data.
-//
-// Revision 1.8 2007/11/18 19:41:45 sybreon
-// Minor simulation fixes.
-//
-// Revision 1.7 2007/11/14 22:11:41 sybreon
-// Added posedge/negedge bus interface.
-// Modified interrupt test system.
-//
-// Revision 1.6 2007/11/13 23:37:28 sybreon
-// Updated simulation to also check BRI 0x00 instruction.
-//
-// Revision 1.5 2007/11/09 20:51:53 sybreon
-// Added GET/PUT support through a FSL bus.
-//
-// Revision 1.4 2007/11/08 14:18:00 sybreon
-// Parameterised optional components.
-//
-// Revision 1.3 2007/11/05 10:59:31 sybreon
-// Added random seed for simulation.
-//
-// Revision 1.2 2007/11/02 19:16:10 sybreon
-// Added interrupt simulation.
-// Changed "human readable" simulation output.
-//
-// Revision 1.1 2007/11/02 03:25:45 sybreon
-// New EDK 3.2 compatible design with optional barrel-shifter and multiplier.
-// Fixed various minor data hazard bugs.
-// Code compatible with -O0/1/2/3/s generated code.
-//
+/* $Id: edk32.v,v 1.12 2007/12/23 20:40:51 sybreon Exp $
+**
+** AEMB EDK 3.2 Compatible Core TEST
+** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <address@hidden>
+**
+** This file is part of AEMB.
+**
+** AEMB is free software: you can redistribute it and/or modify it
+** under the terms of the GNU Lesser General Public License as
+** published by the Free Software Foundation, either version 3 of the
+** License, or (at your option) any later version.
+**
+** AEMB is distributed in the hope that it will be useful, but WITHOUT
+** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General
+** Public License for more details.
+**
+** You should have received a copy of the GNU Lesser General Public
+** License along with AEMB. If not, see <http://www.gnu.org/licenses/>.
+*/
`define AEMB_SIMULATION_KERNEL
@@ -219,7 +180,7 @@
always @(posedge sys_clk_i) begin
// Interrupt Monitors
- if (!dut.rMSR_IE) begin
+ if (!dut.cpu.rMSR_IE) begin
rnd = $random % 30;
inttime = $stime + 1000 + (rnd*rnd * 10);
end
@@ -232,7 +193,7 @@
$finish;
end
if (dwb_we_o & (dwb_dat_o == "RTNI")) sys_int_i = 0;
- if (dut.regf.fRDWE && (dut.rRD == 5'h0e) && !svc && dut.gena) begin
+ if (dut.cpu.regf.fRDWE && (dut.cpu.rRD == 5'h0e) && !svc &&
dut.cpu.gena) begin
svc = 1;
//$display("\nLATENCY: ", ($stime - inttime)/10);
end
@@ -255,7 +216,7 @@
// INTERNAL WIRING ////////////////////////////////////////////////////
- aeMB_edk32 #(16,16)
+ aeMB_sim #(16,16)
dut (
.sys_int_i(sys_int_i),
.dwb_ack_i(dwb_ack_i),
@@ -282,3 +243,46 @@
);
endmodule // edk32
+
+/*
+ $Log: edk32.v,v $
+ Revision 1.12 2007/12/23 20:40:51 sybreon
+ Abstracted simulation kernel (aeMB_sim) to split simulation models from
synthesis models.
+
+ Revision 1.11 2007/12/11 00:44:31 sybreon
+ Modified for AEMB2
+
+ Revision 1.10 2007/11/30 17:08:30 sybreon
+ Moved simulation kernel into code.
+
+ Revision 1.9 2007/11/20 18:36:00 sybreon
+ Removed unnecessary byte acrobatics with VMEM data.
+
+ Revision 1.8 2007/11/18 19:41:45 sybreon
+ Minor simulation fixes.
+
+ Revision 1.7 2007/11/14 22:11:41 sybreon
+ Added posedge/negedge bus interface.
+ Modified interrupt test system.
+
+ Revision 1.6 2007/11/13 23:37:28 sybreon
+ Updated simulation to also check BRI 0x00 instruction.
+
+ Revision 1.5 2007/11/09 20:51:53 sybreon
+ Added GET/PUT support through a FSL bus.
+
+ Revision 1.4 2007/11/08 14:18:00 sybreon
+ Parameterised optional components.
+
+ Revision 1.3 2007/11/05 10:59:31 sybreon
+ Added random seed for simulation.
+
+ Revision 1.2 2007/11/02 19:16:10 sybreon
+ Added interrupt simulation.
+ Changed "human readable" simulation output.
+
+ Revision 1.1 2007/11/02 03:25:45 sybreon
+ New EDK 3.2 compatible design with optional barrel-shifter and multiplier.
+ Fixed various minor data hazard bugs.
+ Code compatible with -O0/1/2/3/s generated code.
+ */
\ No newline at end of file
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- [Commit-gnuradio] r7307 - in usrp2/trunk/fpga/opencores/aemb: doc/CVS sim/CVS sim/verilog sim/verilog/CVS,
matt <=