[Commit-gnuradio] r7214 - usrp2/trunk/fpga/sdr_lib

[matt]

Author: matt
Date: 2007-12-17 00:23:56 -0700 (Mon, 17 Dec 2007)
New Revision: 7214

Modified:
   usrp2/trunk/fpga/sdr_lib/rx_control.v
Log:
cleanups and debugging aids


Modified: usrp2/trunk/fpga/sdr_lib/rx_control.v
===================================================================
--- usrp2/trunk/fpga/sdr_lib/rx_control.v       2007-12-17 07:19:54 UTC (rev 
7213)
+++ usrp2/trunk/fpga/sdr_lib/rx_control.v       2007-12-17 07:23:56 UTC (rev 
7214)
@@ -27,8 +27,14 @@
      output [31:0] debug_rx
      );
 
-   wire [31:0] new_time, new_command;
-   wire        sc_pre1, store_command, clear_overrun;
+   wire [31:0]            new_time, new_command;
+   wire           sc_pre1, clear_overrun;
+   wire [31:0]            rcvtime_pre;
+   reg [31:0]     rcvtime;
+   wire [8:0]     lines_per_frame;
+   wire [22:0]            numlines;
+   wire           full_ctrl, read_ctrl, empty_ctrl, write_ctrl;
+
    setting_reg #(.my_addr(`DSP_CORE_RX_BASE+3)) sr_3
      (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
       .in(set_data),.out(new_time),.changed(sc_pre1));
@@ -44,23 +50,15 @@
    reg                sc_pre2;
    always @(posedge clk)
      sc_pre2 <= sc_pre1;
-   assign      store_command = sc_pre1 & ~sc_pre2;
+   assign      write_ctrl = sc_pre1 & ~sc_pre2;
    
-   wire [31:0] rcvtime_pre;
-   reg [31:0]  rcvtime;
-   wire [8:0]  lines_per_frame;
-   wire [22:0] numlines;
-   wire        full_ctrl, read_ctrl, empty_ctrl;
-
    shortfifo #(.WIDTH(64)) commandfifo
      (.clk(clk),.rst(rst),.clear(clear_overrun),
-      .datain({new_time,new_command}), .write(store_command), .full(full_ctrl),
+      .datain({new_time,new_command}), .write(write_ctrl), .full(full_ctrl),
       .dataout({rcvtime_pre,numlines,lines_per_frame}), .read(read_ctrl), 
.empty(empty_ctrl) );
 
    // Buffer interface to internal FIFO
    wire    write, full, read, empty;
-   reg            xfer_active;
-   reg            sop_i, eop_i;
    wire    sop_o, eop_o;
 
    reg            xfer_state;
@@ -68,24 +66,28 @@
    localparam XFER_GO = 1'b1;
 
    always @(posedge clk)
-     if(rst) xfer_state <= XFER_IDLE;
+     if(rst)
+       xfer_state <= XFER_IDLE;
      else
-       case(xfer_state)
-        XFER_IDLE :
-          if(wr_ready_i)
-            xfer_state <= XFER_GO;
-        XFER_GO :
-          if((eop_o | wr_full_i) & wr_write_o)
+       if(clear_overrun)
+        xfer_state <= XFER_IDLE;
+       else
+        case(xfer_state)
+          XFER_IDLE :
+            if(wr_ready_i)
+              xfer_state <= XFER_GO;
+          XFER_GO :
+            if((eop_o | wr_full_i) & wr_write_o)
+              xfer_state <= XFER_IDLE;
+          default :
             xfer_state <= XFER_IDLE;
-        default :
-          xfer_state <= XFER_IDLE;
-       endcase // case(xfer_state)
-
+        endcase // case(xfer_state)
+   
    assign     wr_write_o = (xfer_state == XFER_GO) & ~empty;
    assign     wr_done_o = (eop_o & wr_write_o);
    assign     wr_error_o = 0;   // FIXME add check here for eop if we have 
wr_full_i once we have IBS
 
-   assign     read = wr_write_o;   // FIXME  what if there is junk between 
packets?
+   assign     read = wr_write_o | (~empty & ~sop_o);   // FIXME  what if there 
is junk between packets?
 
    wire [33:0] fifo_line;
    // Internal FIFO, size 9 is 2K, size 10 is 4K
@@ -112,58 +114,69 @@
  
    always @(posedge clk)
      if(rst)
-       ibs_state <= IBS_IDLE;
+       begin
+         ibs_state <= IBS_IDLE;
+         lines_left <= 0;
+         lines_left_frame <= 0;
+         rcvtime <= 0;
+       end
      else
-       case(ibs_state)
-        IBS_IDLE :
-          if(~empty_ctrl)
-            begin
-               lines_left <= numlines;
-               lines_left_frame <= lines_per_frame;
-               rcvtime <= rcvtime_pre;
-               ibs_state <= IBS_WAITING;
-            end
-        IBS_WAITING :
-          if(go_now)
-            ibs_state <= IBS_FIRSTLINE;
-          else if(too_late)
-            ibs_state <= IBS_OVERRUN;
-          //else if(ibs_reset)
-          //  ibs_state <= IBS_IDLE;
-        IBS_FIRSTLINE :
-          if(full | strobe)
-            ibs_state <= IBS_OVERRUN;
-          else
-            ibs_state <= IBS_RUNNING;
-        IBS_RUNNING :
-          if(strobe)
-            if(full)
+       if(clear_overrun)
+        begin
+         ibs_state <= IBS_IDLE;
+         lines_left <= 0;
+         lines_left_frame <= 0;
+         rcvtime <= 0;
+        end
+       else 
+        case(ibs_state)
+          IBS_IDLE :
+            if(~empty_ctrl)
+              begin
+                 lines_left <= numlines;
+                 lines_left_frame <= lines_per_frame;
+                 rcvtime <= rcvtime_pre;
+                 ibs_state <= IBS_WAITING;
+              end
+          IBS_WAITING :
+            if(go_now)
+              ibs_state <= IBS_FIRSTLINE;
+            else if(too_late)
               ibs_state <= IBS_OVERRUN;
+          IBS_FIRSTLINE :
+            if(full | strobe)
+              ibs_state <= IBS_OVERRUN;
             else
-              begin
-                 lines_left <= lines_left - 1;
-                 if(lines_left == 1)
-                   ibs_state <= IBS_IDLE;
-                 else if(lines_left_frame == 1)
-                   begin
-                      lines_left_frame <= lines_per_frame;
-                      ibs_state <= IBS_FIRSTLINE;
-                   end
-                 else
-                   lines_left_frame <= lines_left_frame - 1;
-              end // else: !if(full)
-        IBS_OVERRUN :
-          if(clear_overrun)
-            ibs_state <= IBS_IDLE;
-       endcase // case(ibs_state)
+              ibs_state <= IBS_RUNNING;
+          IBS_RUNNING :
+            if(strobe)
+              if(full)
+                ibs_state <= IBS_OVERRUN;
+              else
+                begin
+                   lines_left <= lines_left - 1;
+                   if(lines_left == 1)
+                     ibs_state <= IBS_IDLE;
+                   else if(lines_left_frame == 1)
+                     begin
+                        lines_left_frame <= lines_per_frame;
+                        ibs_state <= IBS_FIRSTLINE;
+                     end
+                   else
+                     lines_left_frame <= lines_left_frame - 1;
+                end // else: !if(full)
+        endcase // case(ibs_state)
    
    assign fifo_line = (ibs_state == IBS_FIRSTLINE) ? {1'b1,1'b0,master_time} :
-         {1'b0,((lines_left==1)|(lines_left_frame==1)),sample};
-
-   assign  write = ((ibs_state == IBS_FIRSTLINE) | strobe) & ~full;  // & 
(ibs_state == IBS_RUNNING) should strobe only when running
-   assign  overrun = (ibs_state == IBS_OVERRUN);
-   assign  run = (ibs_state == IBS_RUNNING) | (ibs_state == IBS_FIRSTLINE);
-   assign  read_ctrl = (ibs_state == IBS_IDLE) & ~empty_ctrl;
-
-   assign  debug_rx = {24'd0, sc_pre1, clear_overrun, go_now, too_late, 
overrun, ibs_state[2:0] };
+                     {1'b0,((lines_left==1)|(lines_left_frame==1)),sample};
+   
+   assign write = ((ibs_state == IBS_FIRSTLINE) | strobe) & ~full;  // & 
(ibs_state == IBS_RUNNING) should strobe only when running
+   assign overrun = (ibs_state == IBS_OVERRUN);
+   assign run = (ibs_state == IBS_RUNNING) | (ibs_state == IBS_FIRSTLINE);
+   assign read_ctrl = (ibs_state == IBS_IDLE) & ~empty_ctrl;
+   
+   assign debug_rx = { 8'd0,
+                      wr_write_o, wr_done_o, wr_ready_i, 
wr_full_i,xfer_state,eop_o, sop_o, run,
+                      
write,full,read,empty,write_ctrl,full_ctrl,read_ctrl,empty_ctrl,
+                      sc_pre1, clear_overrun, go_now, too_late, overrun, 
ibs_state[2:0] };
 endmodule // rx_control