[Commit-gnuradio] r7215 - gnuradio/branches/developers/gnychis/inband/usrp/fpga/inband_lib

[gnychis]

Author: gnychis
Date: 2007-12-17 07:53:46 -0700 (Mon, 17 Dec 2007)
New Revision: 7215

Modified:
   
gnuradio/branches/developers/gnychis/inband/usrp/fpga/inband_lib/rx_buffer_inband.v
Log:
Fixing inconsistent tabbing.


Modified: 
gnuradio/branches/developers/gnychis/inband/usrp/fpga/inband_lib/rx_buffer_inband.v
===================================================================
--- 
gnuradio/branches/developers/gnychis/inband/usrp/fpga/inband_lib/rx_buffer_inband.v
 2007-12-17 07:23:56 UTC (rev 7214)
+++ 
gnuradio/branches/developers/gnychis/inband/usrp/fpga/inband_lib/rx_buffer_inband.v
 2007-12-17 14:53:46 UTC (rev 7215)
@@ -58,146 +58,144 @@
                else if (rxstrobe)
                        adctime <= adctime + 1;
      
-    // USB side fifo
-    wire [11:0] rdusedw;
-    wire [11:0] wrusedw;
-       wire [15:0] fifodata;
-       wire [15:0] fifodata_il;
-       reg [15:0] fifodata_16;
-    wire WR;
-    wire have_space;
+  // USB side fifo
+  wire [11:0] rdusedw;
+  wire [11:0] wrusedw;
+  wire [15:0] fifodata;
+  wire [15:0] fifodata_il;
+  reg [15:0] fifodata_16;
+  wire WR;
+  wire have_space;
 
-       assign fifodata_il = fifodata_16;
+  assign fifodata_il = fifodata_16;
 
-    fifo_4kx16_dc      rx_usb_fifo (
-            .aclr ( reset ),
-            .data ( fifodata ),
-            .rdclk ( ~usbclk ),
-            .rdreq ( RD & ~read_count[8] ),
-            .wrclk ( rxclk ),
-            .wrreq ( WR ),
-            .q ( usbdata ),
-            .rdempty (  ),
-            .rdusedw ( rdusedw ),
-            .wrfull (  ),
-            .wrusedw ( wrusedw ) );
+  fifo_4kx16_dc        rx_usb_fifo (
+    .aclr ( reset ),
+    .data ( fifodata ),
+    .rdclk ( ~usbclk ),
+    .rdreq ( RD & ~read_count[8] ),
+    .wrclk ( rxclk ),
+    .wrreq ( WR ),
+    .q ( usbdata ),
+    .rdempty (  ),
+    .rdusedw ( rdusedw ),
+    .wrfull (  ),
+    .wrusedw ( wrusedw ) );
     
-     assign have_pkt_rdy = (rdusedw >= 12'd256);
-     assign have_space = (wrusedw < 12'd760);
+  assign have_pkt_rdy = (rdusedw >= 12'd256);
+  assign have_space = (wrusedw < 12'd760);
         
-        // Rx side fifos
-        wire chan_rdreq;
-        wire [15:0] chan_fifodata;
-        wire [9:0] chan_usedw;
-        wire [NUM_CHAN:0] chan_empty;
-        wire [3:0] rd_select;
-        wire [NUM_CHAN:0] rx_full;
+  // Rx side fifos
+  wire chan_rdreq;
+  wire [15:0] chan_fifodata;
+  wire [9:0] chan_usedw;
+  wire [NUM_CHAN:0] chan_empty;
+  wire [3:0] rd_select;
+  wire [NUM_CHAN:0] rx_full;
         
-        packet_builder #(NUM_CHAN) rx_pkt_builer (
-            .rxclk ( rxclk ),
-            .reset ( reset ),
-            .adctime ( adctime ),
-            .channels ( 4'd1 ), //need to be tested and changed to channels 
-            .chan_rdreq ( chan_rdreq ),
-            .chan_fifodata ( chan_fifodata ),
-            .chan_empty ( chan_empty ),
-            .rd_select ( rd_select ),
-            .chan_usedw ( chan_usedw ),
-            .WR ( WR ),
-            .fifodata ( fifodata ),
-            .have_space ( have_space ),
-             .rssi_0(rssi_0), .rssi_1(rssi_1),
-             .rssi_2(rssi_2),.rssi_3(rssi_3), .debugbus(debug),
-             .underrun(tx_underrun));
+  packet_builder #(NUM_CHAN) rx_pkt_builer (
+    .rxclk ( rxclk ),
+    .reset ( reset ),
+    .adctime ( adctime ),
+    .channels ( 4'd1 ), //need to be tested and changed to channels 
+    .chan_rdreq ( chan_rdreq ),
+    .chan_fifodata ( chan_fifodata ),
+    .chan_empty ( chan_empty ),
+    .rd_select ( rd_select ),
+    .chan_usedw ( chan_usedw ),
+    .WR ( WR ),
+    .fifodata ( fifodata ),
+    .have_space ( have_space ),
+      .rssi_0(rssi_0), .rssi_1(rssi_1),
+      .rssi_2(rssi_2),.rssi_3(rssi_3), .debugbus(debug),
+      .underrun(tx_underrun));
         
-        // Detect overrun
+  // Detect overrun
+  always @(posedge rxclk)
+    if(reset)
+      rx_overrun <= 1'b0;
+    else if(rx_full[0])
+      rx_overrun <= 1'b1;
+    else if(clear_status)
+      rx_overrun <= 1'b0;
 
-    always @(posedge rxclk)
-        if(reset)
-            rx_overrun <= 1'b0;
-        else if(rx_full[0])
-            rx_overrun <= 1'b1;
-        else if(clear_status)
-            rx_overrun <= 1'b0;
-
                
-        // TODO write this genericly
-        wire [15:0]ch[NUM_CHAN:0];
-        assign ch[0] = ch_0;
+  // TODO write this genericly
+  wire [15:0]ch[NUM_CHAN:0];
+  assign ch[0] = ch_0;
        
-        wire cmd_empty;
+  wire cmd_empty;
        
-    always @(posedge rxclk)
-        if(reset)
-            rx_WR_enabled <= 1;
-        else if(cmd_empty)
-            rx_WR_enabled <= 1;
-        else if(rx_WR_done)
-            rx_WR_enabled <= 0;
+  always @(posedge rxclk)
+    if(reset)
+      rx_WR_enabled <= 1;
+    else if(cmd_empty)
+      rx_WR_enabled <= 1;
+    else if(rx_WR_done)
+      rx_WR_enabled <= 0;
 
-       // Switching of channels
-       reg [3:0] store_next;
-       always @(posedge rxclk)
-               if(reset)
-                       store_next <= #1 4'd0;
-               else if(rxstrobe & (store_next == 0))
-                       store_next <= #1 4'd1;
-               else if(~rx_full & (store_next == 4'd2))
-                       store_next <= #1 4'd0;
-               else if(~rx_full & (store_next != 0))
-                       store_next <= #1 store_next + 4'd1;
+  // Switching of channels
+  reg [3:0] store_next;
+  always @(posedge rxclk)
+  if(reset)
+    store_next <= #1 4'd0;
+  else if(rxstrobe & (store_next == 0))
+    store_next <= #1 4'd1;
+  else if(~rx_full & (store_next == 4'd2))
+    store_next <= #1 4'd0;
+  else if(~rx_full & (store_next != 0))
+    store_next <= #1 store_next + 4'd1;
 
-       always @*
-               case(store_next)
-                       4'd1 : fifodata_16 = ch_0;
-                       4'd2 : fifodata_16 = ch_1;
-                       default: fifodata_16 = 16'hFFFF;
-               endcase
+  always @*
+    case(store_next)
+      4'd1 : fifodata_16 = ch_0;
+      4'd2 : fifodata_16 = ch_1;
+      default: fifodata_16 = 16'hFFFF;
+    endcase
 
-       wire [15:0] dataout [0:NUM_CHAN];
-       wire [9:0]  usedw       [0:NUM_CHAN];
-       wire empty[0:NUM_CHAN];
+  wire [15:0] dataout [0:NUM_CHAN];
+  wire [9:0]  usedw    [0:NUM_CHAN];
+  wire empty[0:NUM_CHAN];
        
-     generate for (i = 0 ; i < NUM_CHAN; i = i + 1)
-       begin : generate_channel_fifos
-       
-       wire rdreq;
+  generate for (i = 0 ; i < NUM_CHAN; i = i + 1)
+    begin : generate_channel_fifos
 
-       assign rdreq = (rd_select == i) & chan_rdreq;
+      wire rdreq;
 
-       fifo_1kx16 rx_chan_fifo (
-                .aclr ( reset ),
-                .clock ( rxclk ),
-                .data ( fifodata_il ),
-                .rdreq ( rdreq ),
-             .wrreq ( ~rx_full[i] & (store_next != 0)),
-                .empty (empty[i]),
-                .full (rx_full[i]),
-                .q ( dataout[i]),
-             .usedw ( usedw[i]),
-             .almost_empty(chan_empty[i])
-       );
-       end
-     endgenerate
+      assign rdreq = (rd_select == i) & chan_rdreq;
+
+      fifo_1kx16 rx_chan_fifo (
+      .aclr ( reset ),
+      .clock ( rxclk ),
+      .data ( fifodata_il ),
+      .rdreq ( rdreq ),
+      .wrreq ( ~rx_full[i] & (store_next != 0)),
+      .empty (empty[i]),
+      .full (rx_full[i]),
+      .q ( dataout[i]),
+      .usedw ( usedw[i]),
+      .almost_empty(chan_empty[i])
+      );
+    end
+  endgenerate
        
-     wire [7:0] debug;
+  wire [7:0] debug;
         
-        fifo_1kx16 rx_cmd_fifo (
-                .aclr ( reset ),
-                .clock ( rxclk ),
-                .data ( rx_databus ),
-                .rdreq ( (rd_select == NUM_CHAN) & chan_rdreq ),
-             .wrreq ( rx_WR & rx_WR_enabled),
-                .empty ( cmd_empty),
-                .full ( rx_full[NUM_CHAN] ),
-                .q ( dataout[NUM_CHAN]),
-             .usedw ( usedw[NUM_CHAN] )
-       );
+  fifo_1kx16 rx_cmd_fifo (
+    .aclr ( reset ),
+    .clock ( rxclk ),
+    .data ( rx_databus ),
+    .rdreq ( (rd_select == NUM_CHAN) & chan_rdreq ),
+    .wrreq ( rx_WR & rx_WR_enabled),
+    .empty ( cmd_empty),
+    .full ( rx_full[NUM_CHAN] ),
+    .q ( dataout[NUM_CHAN]),
+    .usedw ( usedw[NUM_CHAN] )
+  );
        
-       assign chan_empty[NUM_CHAN] = cmd_empty | rx_WR_enabled;
-       assign chan_fifodata = dataout[rd_select];
-       assign chan_usedw = usedw[rd_select];
-       assign debugbus = {4'd0, rxclk, rxstrobe, store_next[3], store_next[1], 
store_next[0]};
-                            
+  assign chan_empty[NUM_CHAN] = cmd_empty | rx_WR_enabled;
+  assign chan_fifodata = dataout[rd_select];
+  assign chan_usedw = usedw[rd_select];
+  assign debugbus = {4'd0, rxclk, rxstrobe, store_next[3], store_next[1], 
store_next[0]};
 
 endmodule