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[Commit-gnuradio] r7113 - in usrp2/trunk/fpga/opencores/aemb/sim: . CVS
|
From: |
matt |
|
Subject: |
[Commit-gnuradio] r7113 - in usrp2/trunk/fpga/opencores/aemb/sim: . CVS verilog verilog/CVS |
|
Date: |
Tue, 11 Dec 2007 20:25:54 -0700 (MST) |
Author: matt
Date: 2007-12-11 20:25:53 -0700 (Tue, 11 Dec 2007)
New Revision: 7113
Added:
usrp2/trunk/fpga/opencores/aemb/sim/verilog/aemb2.v
Modified:
usrp2/trunk/fpga/opencores/aemb/sim/CVS/Entries
usrp2/trunk/fpga/opencores/aemb/sim/cversim
usrp2/trunk/fpga/opencores/aemb/sim/iversim
usrp2/trunk/fpga/opencores/aemb/sim/verilog/CVS/Entries
usrp2/trunk/fpga/opencores/aemb/sim/verilog/edk32.v
Log:
catching up, 12/11/07
Modified: usrp2/trunk/fpga/opencores/aemb/sim/CVS/Entries
===================================================================
--- usrp2/trunk/fpga/opencores/aemb/sim/CVS/Entries 2007-12-12 03:24:26 UTC
(rev 7112)
+++ usrp2/trunk/fpga/opencores/aemb/sim/CVS/Entries 2007-12-12 03:25:53 UTC
(rev 7113)
@@ -1,3 +1,3 @@
D/verilog////
-/cversim/1.3/Sat Nov 24 05:11:13 2007//
-/iversim/1.3/Sat Nov 24 05:11:13 2007//
+/cversim/1.5/Wed Dec 12 03:12:13 2007//
+/iversim/1.5/Wed Dec 12 03:12:13 2007//
Modified: usrp2/trunk/fpga/opencores/aemb/sim/cversim
===================================================================
--- usrp2/trunk/fpga/opencores/aemb/sim/cversim 2007-12-12 03:24:26 UTC (rev
7112)
+++ usrp2/trunk/fpga/opencores/aemb/sim/cversim 2007-12-12 03:25:53 UTC (rev
7113)
@@ -1,6 +1,12 @@
#!/bin/sh
-# $Id: cversim,v 1.3 2007/11/05 10:59:31 sybreon Exp $
+# $Id: cversim,v 1.5 2007/12/11 00:44:30 sybreon Exp $
# $Log: cversim,v $
+# Revision 1.5 2007/12/11 00:44:30 sybreon
+# Modified for AEMB2
+#
+# Revision 1.4 2007/11/30 17:08:30 sybreon
+# Moved simulation kernel into code.
+#
# Revision 1.3 2007/11/05 10:59:31 sybreon
# Added random seed for simulation.
#
@@ -13,4 +19,4 @@
#
RANDOM=$(date +%s)
echo "parameter randseed = $RANDOM;" > random.v
-cver -q -w $@ ../rtl/verilog/*.v
+cver -q -w +define+AEMBX_SIMULATION_KERNEL $@ ../rtl/verilog/*.v
Modified: usrp2/trunk/fpga/opencores/aemb/sim/iversim
===================================================================
--- usrp2/trunk/fpga/opencores/aemb/sim/iversim 2007-12-12 03:24:26 UTC (rev
7112)
+++ usrp2/trunk/fpga/opencores/aemb/sim/iversim 2007-12-12 03:25:53 UTC (rev
7113)
@@ -1,6 +1,12 @@
#!/bin/sh
-# $Id: iversim,v 1.3 2007/11/09 20:50:51 sybreon Exp $
+# $Id: iversim,v 1.5 2007/12/11 00:44:30 sybreon Exp $
# $Log: iversim,v $
+# Revision 1.5 2007/12/11 00:44:30 sybreon
+# Modified for AEMB2
+#
+# Revision 1.4 2007/11/30 17:08:30 sybreon
+# Moved simulation kernel into code.
+#
# Revision 1.3 2007/11/09 20:50:51 sybreon
# Added log output to iverilog.log
#
@@ -12,4 +18,4 @@
#
RANDOM=$(date +%s)
echo "parameter randseed = $RANDOM;" > random.v
-iverilog $@ ../rtl/verilog/*.v && vvp -l iverilog.log a.out && rm a.out
+iverilog $@ -DAEMBX_SIMULATION_KERNEL ../rtl/verilog/*.v && vvp -l
iverilog.log a.out && rm a.out
Modified: usrp2/trunk/fpga/opencores/aemb/sim/verilog/CVS/Entries
===================================================================
--- usrp2/trunk/fpga/opencores/aemb/sim/verilog/CVS/Entries 2007-12-12
03:24:26 UTC (rev 7112)
+++ usrp2/trunk/fpga/opencores/aemb/sim/verilog/CVS/Entries 2007-12-12
03:25:53 UTC (rev 7113)
@@ -1,2 +1,3 @@
-/edk32.v/1.9/Mon Nov 26 06:53:03 2007//
+/aemb2.v/1.1/Tue Dec 11 00:44:31 2007//
+/edk32.v/1.11/Wed Dec 12 03:12:13 2007//
D
Added: usrp2/trunk/fpga/opencores/aemb/sim/verilog/aemb2.v
===================================================================
--- usrp2/trunk/fpga/opencores/aemb/sim/verilog/aemb2.v
(rev 0)
+++ usrp2/trunk/fpga/opencores/aemb/sim/verilog/aemb2.v 2007-12-12 03:25:53 UTC
(rev 7113)
@@ -0,0 +1,221 @@
+/* $Id: aemb2.v,v 1.1 2007/12/11 00:44:31 sybreon Exp $
+**
+** AEMB2 TEST BENCH
+**
+** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <address@hidden>
+**
+** This file is part of AEMB.
+**
+** AEMB is free software: you can redistribute it and/or modify it
+** under the terms of the GNU Lesser General Public License as
+** published by the Free Software Foundation, either version 3 of the
+** License, or (at your option) any later version.
+**
+** AEMB is distributed in the hope that it will be useful, but WITHOUT
+** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General
+** Public License for more details.
+**
+** You should have received a copy of the GNU Lesser General Public
+** License along with AEMB. If not, see <http:**www.gnu.org/licenses/>.
+*/
+
+`define AEMB2_SIMULATION_KERNEL
+
+module aemb2 ();
+ parameter IWB=16;
+ parameter DWB=16;
+
+ parameter TXE = 1; ///< thread execution enable
+ parameter LUT = 0; ///< further speed optimisation
+
+ parameter MUL = 1; ///< enable hardware multiplier
+ parameter BSF = 1; ///< enable barrel shifter
+ parameter FSL = 1; ///< enable FSL bus
+ parameter DIV = 0; ///< enable hardware divider
+
+`include "random.v"
+
+ /*AUTOWIRE*/
+ // Beginning of automatic wires (for undeclared instantiated-module outputs)
+ wire [6:2] cwb_adr_o; // From dut of aeMB2_edk32.v
+ wire [31:0] cwb_dat_o; // From dut of aeMB2_edk32.v
+ wire [3:0] cwb_sel_o; // From dut of aeMB2_edk32.v
+ wire cwb_stb_o; // From dut of
aeMB2_edk32.v
+ wire [1:0] cwb_tga_o; // From dut of aeMB2_edk32.v
+ wire cwb_wre_o; // From dut of
aeMB2_edk32.v
+ wire [DWB-1:2] dwb_adr_o; // From dut of aeMB2_edk32.v
+ wire dwb_cyc_o; // From dut of
aeMB2_edk32.v
+ wire [31:0] dwb_dat_o; // From dut of aeMB2_edk32.v
+ wire [3:0] dwb_sel_o; // From dut of aeMB2_edk32.v
+ wire dwb_stb_o; // From dut of
aeMB2_edk32.v
+ wire dwb_wre_o; // From dut of
aeMB2_edk32.v
+ wire [IWB-1:2] iwb_adr_o; // From dut of aeMB2_edk32.v
+ wire iwb_stb_o; // From dut of
aeMB2_edk32.v
+ wire iwb_wre_o; // From dut of
aeMB2_edk32.v
+ // End of automatics
+ /*AUTOREGINPUT*/
+ // Beginning of automatic reg inputs (for undeclared instantiated-module
inputs)
+ reg cwb_ack_i; // To dut of aeMB2_edk32.v
+ reg dwb_ack_i; // To dut of aeMB2_edk32.v
+ reg iwb_ack_i; // To dut of aeMB2_edk32.v
+ reg sys_clk_i; // To dut of aeMB2_edk32.v
+ reg sys_int_i; // To dut of aeMB2_edk32.v
+ reg sys_rst_i; // To dut of aeMB2_edk32.v
+ // End of automatics
+
+ // INITIAL SETUP //////////////////////////////////////////////////////
+
+ //reg sys_clk_i, sys_rst_i, sys_int_i, sys_exc_i;
+ reg svc;
+ integer inttime;
+ integer seed;
+ integer theend;
+
+ always #5 sys_clk_i = ~sys_clk_i;
+
+ initial begin
+ //$dumpfile("dump.vcd");
+ //$dumpvars(1,dut, dut.bpcu);
+ end
+
+ initial begin
+ seed = randseed;
+ theend = 0;
+ svc = 0;
+ sys_clk_i = $random(seed);
+ sys_rst_i = 1;
+ sys_int_i = 0;
+ #50 sys_rst_i = 0;
+ #3500000 $finish;
+ end
+
+ // FAKE MEMORY ////////////////////////////////////////////////////////
+
+ reg [31:0] rom [0:65535];
+ reg [31:0] ram[0:65535];
+ reg [31:0] dwblat;
+ reg [15:2] dadr, iadr;
+
+ wire [31:0] dwb_dat_t = ram[dwb_adr_o];
+ wire [31:0] iwb_dat_i = ram[iadr];
+ wire [31:0] dwb_dat_i = ram[dadr];
+ wire [31:0] cwb_dat_i = cwb_adr_o;
+
+`ifdef POSEDGE
+`else // !`ifdef POSEDGE
+
+ always @(negedge sys_clk_i)
+ if (sys_rst_i) begin
+ /*AUTORESET*/
+ // Beginning of autoreset for uninitialized flops
+ cwb_ack_i <= 1'h0;
+ dwb_ack_i <= 1'h0;
+ iwb_ack_i <= 1'h0;
+ // End of automatics
+ end else begin
+ iwb_ack_i <= #1 iwb_stb_o;
+ dwb_ack_i <= #1 dwb_stb_o;
+ cwb_ack_i <= #1 cwb_stb_o;
+ end // else: !if(sys_rst_i)
+
+ always @(negedge sys_clk_i) begin
+ iadr <= #1 iwb_adr_o;
+ dadr <= #1 dwb_adr_o;
+
+ if (dwb_wre_o & dwb_stb_o) begin
+ case (dwb_sel_o)
+ 4'h1: ram[dwb_adr_o] <= {dwb_dat_t[31:8], dwb_dat_o[7:0]};
+ 4'h2: ram[dwb_adr_o] <= {dwb_dat_t[31:16], dwb_dat_o[15:8],
dwb_dat_t[7:0]};
+ 4'h4: ram[dwb_adr_o] <= {dwb_dat_t[31:24], dwb_dat_o[23:16],
dwb_dat_t[15:0]};
+ 4'h8: ram[dwb_adr_o] <= {dwb_dat_o[31:24], dwb_dat_t[23:0]};
+ 4'h3: ram[dwb_adr_o] <= {dwb_dat_t[31:16], dwb_dat_o[15:0]};
+ 4'hC: ram[dwb_adr_o] <= {dwb_dat_o[31:16], dwb_dat_t[15:0]};
+ 4'hF: ram[dwb_adr_o] <= {dwb_dat_o};
+ endcase // case (dwb_sel_o)
+ end // if (dwb_we_o & dwb_stb_o)
+ end // always @ (negedge sys_clk_i)
+
+`endif // !`ifdef POSEDGE
+
+
+ integer i;
+ initial begin
+ for (i=0;i<65535;i=i+1) begin
+ ram[i] <= $random;
+ end
+ #1 $readmemh("dump.vmem",ram);
+ end
+
+ // DISPLAY OUTPUTS ///////////////////////////////////////////////////
+
+ integer rnd;
+
+ always @(posedge sys_clk_i) begin
+
+ // Pass/Fail Monitors
+ if (dwb_wre_o & (dwb_dat_o == "FAIL")) begin
+ $display("\n\tFAIL");
+ $finish;
+ end
+
+ if (iwb_dat_i == 32'hb8000000) begin
+ theend = theend + 1;
+ end
+
+ if (theend == 5) begin
+ $display("\n\t*** PASSED ALL TESTS ***");
+ $finish;
+ end
+
+ end // always @ (posedge sys_clk_i)
+
+ // INTERNAL WIRING ////////////////////////////////////////////////////
+
+ aeMB2_edk32
+ #(/*AUTOINSTPARAM*/
+ // Parameters
+ .IWB (IWB),
+ .DWB (DWB),
+ .TXE (TXE),
+ .LUT (LUT),
+ .MUL (MUL),
+ .BSF (BSF),
+ .FSL (FSL),
+ .DIV (DIV))
+ dut (/*AUTOINST*/
+ // Outputs
+ .cwb_adr_o (cwb_adr_o[6:2]),
+ .cwb_dat_o (cwb_dat_o[31:0]),
+ .cwb_sel_o (cwb_sel_o[3:0]),
+ .cwb_stb_o (cwb_stb_o),
+ .cwb_tga_o (cwb_tga_o[1:0]),
+ .cwb_wre_o (cwb_wre_o),
+ .dwb_adr_o (dwb_adr_o[DWB-1:2]),
+ .dwb_cyc_o (dwb_cyc_o),
+ .dwb_dat_o (dwb_dat_o[31:0]),
+ .dwb_sel_o (dwb_sel_o[3:0]),
+ .dwb_stb_o (dwb_stb_o),
+ .dwb_wre_o (dwb_wre_o),
+ .iwb_adr_o (iwb_adr_o[IWB-1:2]),
+ .iwb_stb_o (iwb_stb_o),
+ .iwb_wre_o (iwb_wre_o),
+ // Inputs
+ .cwb_ack_i (cwb_ack_i),
+ .cwb_dat_i (cwb_dat_i[31:0]),
+ .dwb_ack_i (dwb_ack_i),
+ .dwb_dat_i (dwb_dat_i[31:0]),
+ .iwb_ack_i (iwb_ack_i),
+ .iwb_dat_i (iwb_dat_i[31:0]),
+ .sys_clk_i (sys_clk_i),
+ .sys_int_i (sys_int_i),
+ .sys_rst_i (sys_rst_i));
+
+endmodule // edk32
+
+/* $Log $ */
+
+// Local Variables:
+// verilog-library-directories:("." "../../rtl/verilog/")
+// verilog-library-files:("")
+// End:
\ No newline at end of file
Modified: usrp2/trunk/fpga/opencores/aemb/sim/verilog/edk32.v
===================================================================
--- usrp2/trunk/fpga/opencores/aemb/sim/verilog/edk32.v 2007-12-12 03:24:26 UTC
(rev 7112)
+++ usrp2/trunk/fpga/opencores/aemb/sim/verilog/edk32.v 2007-12-12 03:25:53 UTC
(rev 7113)
@@ -1,4 +1,4 @@
-// $Id: edk32.v,v 1.9 2007/11/20 18:36:00 sybreon Exp $
+// $Id: edk32.v,v 1.11 2007/12/11 00:44:31 sybreon Exp $
//
// AEMB EDK 3.2 Compatible Core TEST
//
@@ -20,6 +20,12 @@
// License along with AEMB. If not, see <http://www.gnu.org/licenses/>.
//
// $Log: edk32.v,v $
+// Revision 1.11 2007/12/11 00:44:31 sybreon
+// Modified for AEMB2
+//
+// Revision 1.10 2007/11/30 17:08:30 sybreon
+// Moved simulation kernel into code.
+//
// Revision 1.9 2007/11/20 18:36:00 sybreon
// Removed unnecessary byte acrobatics with VMEM data.
//
@@ -52,8 +58,10 @@
// Code compatible with -O0/1/2/3/s generated code.
//
+`define AEMB_SIMULATION_KERNEL
+
module edk32 ();
-
+
`include "random.v"
// INITIAL SETUP //////////////////////////////////////////////////////
@@ -127,7 +135,6 @@
assign dwb_dat_i = ram[dadr];
assign fsl_dat_i = fsl_adr_o;
-//`define POSEDGE
`ifdef POSEDGE
always @(posedge sys_clk_i)
@@ -142,7 +149,7 @@
iwb_ack_i <= #1 iwb_stb_o ^ iwb_ack_i;
dwb_ack_i <= #1 dwb_stb_o ^ dwb_ack_i;
fsl_ack_i <= #1 fsl_stb_o ^ fsl_ack_i;
- end
+ end // else: !if(sys_rst_i)
always @(posedge sys_clk_i) begin
iadr <= #1 iwb_adr_o;
@@ -159,7 +166,7 @@
4'hF: ram[dwb_adr_o] <= {dwb_dat_o};
endcase // case (dwb_sel_o)
end // if (dwb_we_o & dwb_stb_o)
- end // always @ (negedge sys_clk_i)
+ end // always @ (posedge sys_clk_i)
`else // !`ifdef POSEDGE
@@ -175,7 +182,7 @@
iwb_ack_i <= #1 iwb_stb_o;
dwb_ack_i <= #1 dwb_stb_o;
fsl_ack_i <= #1 fsl_stb_o;
- end
+ end // else: !if(sys_rst_i)
always @(negedge sys_clk_i) begin
iadr <= #1 iwb_adr_o;
@@ -202,13 +209,11 @@
for (i=0;i<65535;i=i+1) begin
ram[i] <= $random;
end
- #1 $readmemh("dump.rom",ram);
+ #1 $readmemh("dump.vmem",ram);
end
// DISPLAY OUTPUTS ///////////////////////////////////////////////////
- //assign dut.rRESULT = dut.rSIMM;
-
integer rnd;
always @(posedge sys_clk_i) begin
@@ -247,190 +252,7 @@
$finish;
end
end // always @ (posedge sys_clk_i)
-
-
- always @(posedge sys_clk_i) if (dut.gena) begin
- $write ("\n", ($stime/10));
- $writeh ("\tPC=", {iwb_adr_o,2'd0});
-
- // DECODE
- $writeh ("\t");
-
- case ({dut.rBRA, dut.rDLY})
- 2'b00: $write(" ");
- 2'b01: $write(".");
- 2'b10: $write("-");
- 2'b11: $write("+");
- endcase // case ({dut.rBRA, dut.rDLY})
-
- case (dut.rOPC)
- 6'o00: if (dut.rRD == 0) $write(" "); else $write("ADD");
- 6'o01: $write("RSUB");
- 6'o02: $write("ADDC");
- 6'o03: $write("RSUBC");
- 6'o04: $write("ADDK");
- 6'o05: case (dut.rIMM[1:0])
- 2'o0: $write("RSUBK");
- 2'o1: $write("CMP");
- 2'o3: $write("CMPU");
- default: $write("XXX");
- endcase // case (dut.rIMM[1:0])
- 6'o06: $write("ADDKC");
- 6'o07: $write("RSUBKC");
-
- 6'o10: $write("ADDI");
- 6'o11: $write("RSUBI");
- 6'o12: $write("ADDIC");
- 6'o13: $write("RSUBIC");
- 6'o14: $write("ADDIK");
- 6'o15: $write("RSUBIK");
- 6'o16: $write("ADDIKC");
- 6'o17: $write("RSUBIKC");
-
- 6'o20: $write("MUL");
- 6'o21: case (dut.rALT[10:9])
- 2'o0: $write("BSRL");
- 2'o1: $write("BSRA");
- 2'o2: $write("BSLL");
- default: $write("XXX");
- endcase // case (dut.rALT[10:9])
- 6'o22: $write("IDIV");
-
- 6'o30: $write("MULI");
- 6'o31: case (dut.rALT[10:9])
- 2'o0: $write("BSRLI");
- 2'o1: $write("BSRAI");
- 2'o2: $write("BSLLI");
- default: $write("XXX");
- endcase // case (dut.rALT[10:9])
- 6'o33: case (dut.rRB[4:2])
- 3'o0: $write("GET");
- 3'o4: $write("PUT");
- 3'o2: $write("NGET");
- 3'o6: $write("NPUT");
- 3'o1: $write("CGET");
- 3'o5: $write("CPUT");
- 3'o3: $write("NCGET");
- 3'o7: $write("NCPUT");
- endcase // case (dut.rRB[4:2])
-
-
- 6'o40: $write("OR");
- 6'o41: $write("AND");
- 6'o42: if (dut.rRD == 0) $write(" "); else $write("XOR");
- 6'o43: $write("ANDN");
- 6'o44: case (dut.rIMM[6:5])
- 2'o0: $write("SRA");
- 2'o1: $write("SRC");
- 2'o2: $write("SRL");
- 2'o3: if (dut.rIMM[0]) $write("SEXT16"); else $write("SEXT8");
- endcase // case (dut.rIMM[6:5])
-
- 6'o45: $write("MOV");
- 6'o46: case (dut.rRA[3:2])
- 3'o0: $write("BR");
- 3'o1: $write("BRL");
- 3'o2: $write("BRA");
- 3'o3: $write("BRAL");
- endcase // case (dut.rRA[3:2])
-
- 6'o47: case (dut.rRD[2:0])
- 3'o0: $write("BEQ");
- 3'o1: $write("BNE");
- 3'o2: $write("BLT");
- 3'o3: $write("BLE");
- 3'o4: $write("BGT");
- 3'o5: $write("BGE");
- default: $write("XXX");
- endcase // case (dut.rRD[2:0])
-
- 6'o50: $write("ORI");
- 6'o51: $write("ANDI");
- 6'o52: $write("XORI");
- 6'o53: $write("ANDNI");
- 6'o54: $write("IMMI");
- 6'o55: case (dut.rRD[1:0])
- 2'o0: $write("RTSD");
- 2'o1: $write("RTID");
- 2'o2: $write("RTBD");
- default: $write("XXX");
- endcase
- 6'o56: case (dut.rRA[3:2])
- 3'o0: $write("BRI");
- 3'o1: $write("BRLI");
- 3'o2: $write("BRAI");
- 3'o3: $write("BRALI");
- endcase // case (dut.rRA[3:2])
- 6'o57: case (dut.rRD[2:0])
- 3'o0: $write("BEQI");
- 3'o1: $write("BNEI");
- 3'o2: $write("BLTI");
- 3'o3: $write("BLEI");
- 3'o4: $write("BGTI");
- 3'o5: $write("BGEI");
- default: $write("XXX");
- endcase // case (dut.rRD[2:0])
-
- 6'o60: $write("LBU");
- 6'o61: $write("LHU");
- 6'o62: $write("LW");
- 6'o64: $write("SB");
- 6'o65: $write("SH");
- 6'o66: $write("SW");
-
- 6'o70: $write("LBUI");
- 6'o71: $write("LHUI");
- 6'o72: $write("LWI");
- 6'o74: $write("SBI");
- 6'o75: $write("SHI");
- 6'o76: $write("SWI");
-
- default: $write("XXX");
- endcase // case (dut.rOPC)
-
- case (dut.rOPC[3])
- 1'b1: $writeh("\tr",dut.rRD,", r",dut.rRA,", h",dut.rIMM);
- 1'b0: $writeh("\tr",dut.rRD,", r",dut.rRA,", r",dut.rRB," ");
- endcase // case (dut.rOPC[3])
-
-
- // ALU
- $write("\t");
- //$writeh(" I=",dut.rSIMM);
- $writeh(" A=",dut.xecu.rOPA);
- $writeh(" B=",dut.xecu.rOPB);
-
- case (dut.rMXALU)
- 3'o0: $write(" ADD");
- 3'o1: $write(" LOG");
- 3'o2: $write(" SFT");
- 3'o3: $write(" MOV");
- 3'o4: $write(" MUL");
- 3'o5: $write(" BSF");
- default: $write(" XXX");
- endcase // case (dut.rMXALU)
- $writeh("=h",dut.xecu.xRESULT);
-
- // WRITEBACK
- $writeh("\tSR=", {dut.xecu.rMSR_BIP, dut.xecu.rMSR_C, dut.xecu.rMSR_IE,
dut.xecu.rMSR_BE}," ");
-
- if (dut.regf.fRDWE) begin
- case (dut.rMXDST)
- 2'o2: begin
- if (dut.dwb_stb_o)
$writeh("R",dut.rRW,"=RAM(h",dut.regf.xWDAT,")");
- if (dut.fsl_stb_o)
$writeh("R",dut.rRW,"=FSL(h",dut.regf.xWDAT,")");
- end
- 2'o1: $writeh("R",dut.rRW,"=LNK(h",dut.regf.xWDAT,")");
- 2'o0: $writeh("R",dut.rRW,"=ALU(h",dut.regf.xWDAT,")");
- endcase // case (dut.rMXDST)
- end
-
- // STORE
- if (dwb_stb_o & dwb_we_o)
$writeh("RAM(",{dwb_adr_o,2'd0},")=",dwb_dat_o,":",dwb_sel_o);
-
- end // if (dut.gena)
-
// INTERNAL WIRING ////////////////////////////////////////////////////
aeMB_edk32 #(16,16)
@@ -459,8 +281,4 @@
.sys_rst_i(sys_rst_i)
);
-
-
-
-
endmodule // edk32
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