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[Commit-gnuradio] r7114 - in usrp2/trunk/fpga/opencores/aemb/rtl/verilog
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From: |
matt |
|
Subject: |
[Commit-gnuradio] r7114 - in usrp2/trunk/fpga/opencores/aemb/rtl/verilog: . CVS |
|
Date: |
Tue, 11 Dec 2007 20:29:43 -0700 (MST) |
Author: matt
Date: 2007-12-11 20:29:43 -0700 (Tue, 11 Dec 2007)
New Revision: 7114
Modified:
usrp2/trunk/fpga/opencores/aemb/rtl/verilog/CVS/Entries
usrp2/trunk/fpga/opencores/aemb/rtl/verilog/aeMB_ctrl.v
usrp2/trunk/fpga/opencores/aemb/rtl/verilog/aeMB_edk32.v
usrp2/trunk/fpga/opencores/aemb/rtl/verilog/aeMB_xecu.v
Log:
catch up with code cleanups, plus he put some debug stuff in there. 12/11/07
Modified: usrp2/trunk/fpga/opencores/aemb/rtl/verilog/CVS/Entries
===================================================================
--- usrp2/trunk/fpga/opencores/aemb/rtl/verilog/CVS/Entries 2007-12-12
03:25:53 UTC (rev 7113)
+++ usrp2/trunk/fpga/opencores/aemb/rtl/verilog/CVS/Entries 2007-12-12
03:29:43 UTC (rev 7114)
@@ -1,8 +1,15 @@
/aeMB_bpcu.v/1.4/Sat Nov 24 05:11:03 2007//
/aeMB_core.v/1.9/Mon Nov 26 06:53:03 2007//
-/aeMB_edk32.v/1.10/Mon Nov 26 06:53:03 2007//
/aeMB_ibuf.v/1.7/Mon Nov 26 06:53:03 2007//
/aeMB_regf.v/1.3/Sat Nov 24 05:11:03 2007//
-/aeMB_xecu.v/1.8/Mon Nov 26 06:53:03 2007//
-/aeMB_ctrl.v/1.9/Mon Nov 26 06:56:30 2007//
+/aeMB2_aslu.v/1.1/Tue Dec 11 00:43:17 2007//
+/aeMB2_bpcu.v/1.1/Tue Dec 11 00:43:17 2007//
+/aeMB2_edk32.v/1.2/Tue Dec 11 00:43:17 2007//
+/aeMB2_idmx.v/1.1/Tue Dec 11 00:43:17 2007//
+/aeMB2_opmx.v/1.1/Tue Dec 11 00:43:17 2007//
+/aeMB2_regf.v/1.1/Tue Dec 11 00:43:17 2007//
+/aeMB2_sysc.v/1.1/Tue Dec 11 00:43:17 2007//
+/aeMB_ctrl.v/1.10/Wed Dec 12 03:12:13 2007//
+/aeMB_edk32.v/1.11/Wed Dec 12 03:12:13 2007//
+/aeMB_xecu.v/1.9/Wed Dec 12 03:12:13 2007//
D
Modified: usrp2/trunk/fpga/opencores/aemb/rtl/verilog/aeMB_ctrl.v
===================================================================
--- usrp2/trunk/fpga/opencores/aemb/rtl/verilog/aeMB_ctrl.v 2007-12-12
03:25:53 UTC (rev 7113)
+++ usrp2/trunk/fpga/opencores/aemb/rtl/verilog/aeMB_ctrl.v 2007-12-12
03:29:43 UTC (rev 7114)
@@ -1,4 +1,4 @@
-// $Id: aeMB_ctrl.v,v 1.9 2007/11/15 09:26:43 sybreon Exp $
+// $Id: aeMB_ctrl.v,v 1.10 2007/11/30 16:44:40 sybreon Exp $
//
// AEMB CONTROL UNIT
//
@@ -20,6 +20,9 @@
// License along with AEMB. If not, see <http://www.gnu.org/licenses/>.
//
// $Log: aeMB_ctrl.v,v $
+// Revision 1.10 2007/11/30 16:44:40 sybreon
+// Minor code cleanup.
+//
// Revision 1.9 2007/11/15 09:26:43 sybreon
// Fixed minor typo causing synthesis failure.
//
@@ -66,10 +69,7 @@
output [1:0] rMXSRC, rMXTGT, rMXALT;
output [2:0] rMXALU;
output [4:0] rRW;
- //output rDWBSTB;
- //output rFSLSTB;
- //input [1:0] rXCE;
input rDLY;
input [15:0] rIMM;
input [10:0] rALT;
@@ -164,28 +164,6 @@
// --- OPERAND SELECTOR ---------------------------------
- /*
- wire fRDWE = |rRW;
- wire fAFWD_M = (rRW == rRA) & (rMXDST == 2'o2) & fRDWE;
- wire fBFWD_M = (rRW == rRB) & (rMXDST == 2'o2) & fRDWE;
- wire fAFWD_R = (rRW == rRA) & (rMXDST == 2'o0) & fRDWE;
- wire fBFWD_R = (rRW == rRB) & (rMXDST == 2'o0) & fRDWE;
-
- assign rMXSRC = (fBRU | fBCC) ? 2'o3 : // PC
- (fAFWD_M) ? 2'o2: // RAM
- (fAFWD_R) ? 2'o1: // FWD
- 2'o0; // REG
-
- assign rMXTGT = (rOPC[3]) ? 2'o3 : // IMM
- (fBFWD_M) ? 2'o2 : // RAM
- (fBFWD_R) ? 2'o1 : // FWD
- 2'o0; // REG
-
- assign rMXALT = (fAFWD_M) ? 2'o2 : // RAM
- (fAFWD_R) ? 2'o1 : // FWD
- 2'o0; // REG
- */
-
wire wRDWE = |xRW;
wire wAFWD_M = (xRW == wRA) & (xMXDST == 2'o2) & wRDWE;
wire wBFWD_M = (xRW == wRB) & (xMXDST == 2'o2) & wRDWE;
@@ -214,24 +192,10 @@
xMXALT <= (wAFWD_M) ? 2'o2 : // RAM
(wAFWD_R) ? 2'o1 : // FWD
2'o0; // REG
- end
+ end // else: !if(rBRA)
// --- ALU CONTROL ---------------------------------------
- /*
- reg [2:0] rMXALU;
- always @(fBRA or fBSF or fDIV or fLOG or fMOV or fMUL
- or fSFT) begin
- rMXALU <= (fBRA | fMOV) ? 3'o3 :
- (fSFT) ? 3'o2 :
- (fLOG) ? 3'o1 :
- (fMUL) ? 3'o4 :
- (fBSF) ? 3'o5 :
- (fDIV) ? 3'o6 :
- 3'o0;
- end
- */
-
reg [2:0] rMXALU, xMXALU;
always @(/*AUTOSENSE*/rBRA or wBRA or wBSF or wDIV or wLOG or wMOV
@@ -250,7 +214,7 @@
(wBSF) ? 3'o5 :
(wDIV) ? 3'o6 :
3'o0;
- end
+ end // else: !if(rBRA)
// --- DELAY SLOT REGISTERS ------------------------------
@@ -265,20 +229,6 @@
xRW <= 5'h0;
// End of automatics
end else begin
- /*
- case (rXCE)
- 2'o2: xMXDST <= 2'o1;
- default: xMXDST <= (fSTR | fRTD | fBCC) ? 2'o3 :
- (fLOD | fGET) ? 2'o2 :
- (fBRU) ? 2'o1 :
- 2'o0;
- endcase
-
- case (rXCE)
- 2'o2: xRW <= 5'd14;
- default: xRW <= rRD;
- endcase
- */
xMXDST <= (fSTR | fRTD | fBCC) ? 2'o3 :
(fLOD | fGET) ? 2'o2 :
(fBRU) ? 2'o1 :
@@ -321,7 +271,7 @@
end else if (fDACK) begin
rDWBSTB <= #1 xDWBSTB;
rDWBWRE <= #1 xDWBWRE;
- end
+ end
// --- FSL WISHBONE -----------------------------------
@@ -372,7 +322,7 @@
rMXTGT <= 2'h0;
rRW <= 5'h0;
// End of automatics
- end else if (gena) begin
+ end else if (gena) begin // if (grst)
//rPCLNK <= #1 xPCLNK;
rMXDST <= #1 xMXDST;
rRW <= #1 xRW;
Modified: usrp2/trunk/fpga/opencores/aemb/rtl/verilog/aeMB_edk32.v
===================================================================
--- usrp2/trunk/fpga/opencores/aemb/rtl/verilog/aeMB_edk32.v 2007-12-12
03:25:53 UTC (rev 7113)
+++ usrp2/trunk/fpga/opencores/aemb/rtl/verilog/aeMB_edk32.v 2007-12-12
03:29:43 UTC (rev 7114)
@@ -1,4 +1,4 @@
-// $Id: aeMB_edk32.v,v 1.10 2007/11/16 21:52:03 sybreon Exp $
+// $Id: aeMB_edk32.v,v 1.11 2007/11/30 17:08:29 sybreon Exp $
//
// AEMB EDK 3.2 Compatible Core
//
@@ -20,6 +20,9 @@
// License along with AEMB. If not, see <http://www.gnu.org/licenses/>.
//
// $Log: aeMB_edk32.v,v $
+// Revision 1.11 2007/11/30 17:08:29 sybreon
+// Moved simulation kernel into code.
+//
// Revision 1.10 2007/11/16 21:52:03 sybreon
// Added fsl_tag_o to FSL bus (tag either address or data).
//
@@ -127,10 +130,12 @@
input sys_clk_i;
input sys_rst_i;
-
+
wire grst = sys_rst_i;
wire gclk = sys_clk_i;
wire gena = !((dwb_stb_o ^ dwb_ack_i) | (fsl_stb_o ^
fsl_ack_i) | !iwb_ack_i);
+
+ // --- INSTANTIATIONS -------------------------------------
aeMB_ibuf
ibuf (/*AUTOINST*/
@@ -265,5 +270,204 @@
.grst (grst),
.gena (gena));
+
+ // --- SIMULATION KERNEL ----------------------------------
+ // synopsys translate_off
+
+`ifdef AEMB_SIMULATION_KERNEL
+
+ wire [IW-1:0] iwb_adr = {iwb_adr_o, 2'd0};
+ wire [DW-1:0] dwb_adr = {dwb_adr_o,2'd0};
+ wire [1:0] wBRA = {rBRA, rDLY};
+ wire [3:0] wMSR = {xecu.rMSR_BIP, xecu.rMSR_C, xecu.rMSR_IE,
xecu.rMSR_BE};
+
+ always @(posedge gclk) if (gena) begin
+ $write ("\n", ($stime/10));
+ $writeh (" PC=", iwb_adr );
+ $writeh ("\t");
+
+ case (wBRA)
+ 2'b00: $write(" ");
+ 2'b01: $write(".");
+ 2'b10: $write("-");
+ 2'b11: $write("+");
+ endcase // case (wBRA)
+
+ case (rOPC)
+ 6'o00: if (rRD == 0) $write(" "); else $write("ADD");
+ 6'o01: $write("RSUB");
+ 6'o02: $write("ADDC");
+ 6'o03: $write("RSUBC");
+ 6'o04: $write("ADDK");
+ 6'o05: case (rIMM[1:0])
+ 2'o0: $write("RSUBK");
+ 2'o1: $write("CMP");
+ 2'o3: $write("CMPU");
+ default: $write("XXX");
+ endcase // case (rIMM[1:0])
+ 6'o06: $write("ADDKC");
+ 6'o07: $write("RSUBKC");
+
+ 6'o10: $write("ADDI");
+ 6'o11: $write("RSUBI");
+ 6'o12: $write("ADDIC");
+ 6'o13: $write("RSUBIC");
+ 6'o14: $write("ADDIK");
+ 6'o15: $write("RSUBIK");
+ 6'o16: $write("ADDIKC");
+ 6'o17: $write("RSUBIKC");
+
+ 6'o20: $write("MUL");
+ 6'o21: case (rALT[10:9])
+ 2'o0: $write("BSRL");
+ 2'o1: $write("BSRA");
+ 2'o2: $write("BSLL");
+ default: $write("XXX");
+ endcase // case (rALT[10:9])
+ 6'o22: $write("IDIV");
+
+ 6'o30: $write("MULI");
+ 6'o31: case (rALT[10:9])
+ 2'o0: $write("BSRLI");
+ 2'o1: $write("BSRAI");
+ 2'o2: $write("BSLLI");
+ default: $write("XXX");
+ endcase // case (rALT[10:9])
+ 6'o33: case (rRB[4:2])
+ 3'o0: $write("GET");
+ 3'o4: $write("PUT");
+ 3'o2: $write("NGET");
+ 3'o6: $write("NPUT");
+ 3'o1: $write("CGET");
+ 3'o5: $write("CPUT");
+ 3'o3: $write("NCGET");
+ 3'o7: $write("NCPUT");
+ endcase // case (rRB[4:2])
+
+ 6'o40: $write("OR");
+ 6'o41: $write("AND");
+ 6'o42: if (rRD == 0) $write(" "); else $write("XOR");
+ 6'o43: $write("ANDN");
+ 6'o44: case (rIMM[6:5])
+ 2'o0: $write("SRA");
+ 2'o1: $write("SRC");
+ 2'o2: $write("SRL");
+ 2'o3: if (rIMM[0]) $write("SEXT16"); else $write("SEXT8");
+ endcase // case (rIMM[6:5])
+
+ 6'o45: $write("MOV");
+ 6'o46: case (rRA[3:2])
+ 3'o0: $write("BR");
+ 3'o1: $write("BRL");
+ 3'o2: $write("BRA");
+ 3'o3: $write("BRAL");
+ endcase // case (rRA[3:2])
+
+ 6'o47: case (rRD[2:0])
+ 3'o0: $write("BEQ");
+ 3'o1: $write("BNE");
+ 3'o2: $write("BLT");
+ 3'o3: $write("BLE");
+ 3'o4: $write("BGT");
+ 3'o5: $write("BGE");
+ default: $write("XXX");
+ endcase // case (rRD[2:0])
+
+ 6'o50: $write("ORI");
+ 6'o51: $write("ANDI");
+ 6'o52: $write("XORI");
+ 6'o53: $write("ANDNI");
+ 6'o54: $write("IMMI");
+ 6'o55: case (rRD[1:0])
+ 2'o0: $write("RTSD");
+ 2'o1: $write("RTID");
+ 2'o2: $write("RTBD");
+ default: $write("XXX");
+ endcase // case (rRD[1:0])
+ 6'o56: case (rRA[3:2])
+ 3'o0: $write("BRI");
+ 3'o1: $write("BRLI");
+ 3'o2: $write("BRAI");
+ 3'o3: $write("BRALI");
+ endcase // case (rRA[3:2])
+ 6'o57: case (rRD[2:0])
+ 3'o0: $write("BEQI");
+ 3'o1: $write("BNEI");
+ 3'o2: $write("BLTI");
+ 3'o3: $write("BLEI");
+ 3'o4: $write("BGTI");
+ 3'o5: $write("BGEI");
+ default: $write("XXX");
+ endcase // case (rRD[2:0])
+
+ 6'o60: $write("LBU");
+ 6'o61: $write("LHU");
+ 6'o62: $write("LW");
+ 6'o64: $write("SB");
+ 6'o65: $write("SH");
+ 6'o66: $write("SW");
+
+ 6'o70: $write("LBUI");
+ 6'o71: $write("LHUI");
+ 6'o72: $write("LWI");
+ 6'o74: $write("SBI");
+ 6'o75: $write("SHI");
+ 6'o76: $write("SWI");
+
+ default: $write("XXX");
+ endcase // case (rOPC)
+
+ case (rOPC[3])
+ 1'b1: $writeh("\tr",rRD,", r",rRA,", h",rIMM);
+ 1'b0: $writeh("\tr",rRD,", r",rRA,", r",rRB," ");
+ endcase // case (rOPC[3])
+
+
+ // ALU
+ $write("\t");
+ $writeh(" A=",xecu.rOPA);
+ $writeh(" B=",xecu.rOPB);
+
+ case (rMXALU)
+ 3'o0: $write(" ADD");
+ 3'o1: $write(" LOG");
+ 3'o2: $write(" SFT");
+ 3'o3: $write(" MOV");
+ 3'o4: $write(" MUL");
+ 3'o5: $write(" BSF");
+ default: $write(" XXX");
+ endcase // case (rMXALU)
+ $writeh("=h",xecu.xRESULT);
+
+ // WRITEBACK
+ $writeh("\tSR=", wMSR," ");
+
+ if (regf.fRDWE) begin
+ case (rMXDST)
+ 2'o2: begin
+ if (dwb_stb_o) $writeh("R",rRW,"=RAM(h",regf.xWDAT,")");
+ if (fsl_stb_o) $writeh("R",rRW,"=FSL(h",regf.xWDAT,")");
+ end
+ 2'o1: $writeh("R",rRW,"=LNK(h",regf.xWDAT,")");
+ 2'o0: $writeh("R",rRW,"=ALU(h",regf.xWDAT,")");
+ endcase // case (rMXDST)
+ end
+
+ // STORE
+ if (dwb_stb_o & dwb_wre_o) begin
+ $writeh("RAM(", dwb_adr ,")=", dwb_dat_o);
+ case (dwb_sel_o)
+ 4'hF: $write(":L");
+ 4'h3,4'hC: $write(":W");
+ 4'h1,4'h2,4'h4,4'h8: $write(":B");
+ endcase // case (dwb_sel_o)
+
+ end
+
+ end // if (gena)
+
+`endif // `ifdef AEMB_SIMULATION_KERNEL
+ // synopsys translate_on
+
endmodule // aeMB_edk32
Modified: usrp2/trunk/fpga/opencores/aemb/rtl/verilog/aeMB_xecu.v
===================================================================
--- usrp2/trunk/fpga/opencores/aemb/rtl/verilog/aeMB_xecu.v 2007-12-12
03:25:53 UTC (rev 7113)
+++ usrp2/trunk/fpga/opencores/aemb/rtl/verilog/aeMB_xecu.v 2007-12-12
03:29:43 UTC (rev 7114)
@@ -1,4 +1,4 @@
-// $Id: aeMB_xecu.v,v 1.8 2007/11/16 21:52:03 sybreon Exp $
+// $Id: aeMB_xecu.v,v 1.9 2007/11/30 16:42:51 sybreon Exp $
//
// AEMB MAIN EXECUTION ALU
//
@@ -20,6 +20,9 @@
// License along with AEMB. If not, see <http://www.gnu.org/licenses/>.
//
// $Log: aeMB_xecu.v,v $
+// Revision 1.9 2007/11/30 16:42:51 sybreon
+// Minor code cleanup.
+//
// Revision 1.8 2007/11/16 21:52:03 sybreon
// Added fsl_tag_o to FSL bus (tag either address or data).
//
@@ -75,7 +78,6 @@
output [3:0] rDWBSEL;
output rMSR_IE;
output rMSR_BIP;
- //input [1:0] rXCE;
input [31:0] rREGA, rREGB;
input [1:0] rMXSRC, rMXTGT;
input [4:0] rRA, rRB;
@@ -89,8 +91,6 @@
input [4:0] rRD;
input [31:0] rDWBDI;
input [31:2] rPC;
- //input [31:0] rRES_MUL; // External Multiplier
- //input [31:0] rRES_BSF; // External Barrel Shifter
// SYSTEM
input gclk, grst, gena;
@@ -191,7 +191,8 @@
rOPA;
// --- MULTIPLIER ------------------------------------------
-
+ // TODO: 2 stage multiplier
+
reg [31:0] rRES_MUL;
always @(/*AUTOSENSE*/rOPA or rOPB) begin
rRES_MUL <= (rOPA * rOPB);
@@ -282,10 +283,10 @@
wire fRTID = (rOPC == 6'o55) & rRD[0];
wire fRTBD = (rOPC == 6'o55) & rRD[1];
wire fBRK = ((rOPC == 6'o56) | (rOPC == 6'o66)) & (rRA == 5'hC);
- wire fXCE = ((rOPC == 6'o56) | (rOPC == 6'o66)) & (rRA == 5'hE);
+ wire fINT = ((rOPC == 6'o56) | (rOPC == 6'o66)) & (rRA == 5'hE);
- always @(/*AUTOSENSE*/fMTS or fRTID or fXCE or rMSR_IE or rOPA)
- xMSR_IE <= (fXCE) ? 1'b0 :
+ always @(/*AUTOSENSE*/fINT or fMTS or fRTID or rMSR_IE or rOPA)
+ xMSR_IE <= (fINT) ? 1'b0 :
(fRTID) ? 1'b1 :
(fMTS) ? rOPA[1] :
rMSR_IE;
@@ -374,5 +375,5 @@
rMSR_BIP <= #1 xMSR_BIP;
rFSLADR <= #1 xFSLADR;
end
-
+
endmodule // aeMB_xecu
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- [Commit-gnuradio] r7114 - in usrp2/trunk/fpga/opencores/aemb/rtl/verilog: . CVS,
matt <=