[Commit-gnuradio] r7112 - in usrp2/trunk/fpga/opencores/aemb/sw: . CVS c c/CVS

[matt]

Author: matt
Date: 2007-12-11 20:24:26 -0700 (Tue, 11 Dec 2007)
New Revision: 7112

Added:
   usrp2/trunk/fpga/opencores/aemb/sw/c/libaemb.h
Modified:
   usrp2/trunk/fpga/opencores/aemb/sw/CVS/Entries
   usrp2/trunk/fpga/opencores/aemb/sw/c/CVS/Entries
   usrp2/trunk/fpga/opencores/aemb/sw/c/aeMB_testbench.c
   usrp2/trunk/fpga/opencores/aemb/sw/gccrom
Log:
catching up with new aemb sw library, 12/11/07


Modified: usrp2/trunk/fpga/opencores/aemb/sw/CVS/Entries
===================================================================
--- usrp2/trunk/fpga/opencores/aemb/sw/CVS/Entries      2007-12-11 23:45:06 UTC 
(rev 7111)
+++ usrp2/trunk/fpga/opencores/aemb/sw/CVS/Entries      2007-12-12 03:24:26 UTC 
(rev 7112)
@@ -1,2 +1,2 @@
 D/c////
-/gccrom/1.10/Mon Nov 26 06:53:03 2007//
+/gccrom/1.12/Wed Dec 12 03:12:13 2007//

Modified: usrp2/trunk/fpga/opencores/aemb/sw/c/CVS/Entries
===================================================================
--- usrp2/trunk/fpga/opencores/aemb/sw/c/CVS/Entries    2007-12-11 23:45:06 UTC 
(rev 7111)
+++ usrp2/trunk/fpga/opencores/aemb/sw/c/CVS/Entries    2007-12-12 03:24:26 UTC 
(rev 7112)
@@ -1,2 +1,3 @@
-/aeMB_testbench.c/1.12/Mon Nov 26 06:53:03 2007//
+/aeMB_testbench.c/1.13/Wed Dec 12 03:12:13 2007//
+/libaemb.h/1.1/Tue Dec 11 00:44:04 2007//
 D

Modified: usrp2/trunk/fpga/opencores/aemb/sw/c/aeMB_testbench.c
===================================================================
--- usrp2/trunk/fpga/opencores/aemb/sw/c/aeMB_testbench.c       2007-12-11 
23:45:06 UTC (rev 7111)
+++ usrp2/trunk/fpga/opencores/aemb/sw/c/aeMB_testbench.c       2007-12-12 
03:24:26 UTC (rev 7112)
@@ -1,5 +1,5 @@
 /*
- * $Id: aeMB_testbench.c,v 1.12 2007/11/18 19:41:45 sybreon Exp $
+ * $Id: aeMB_testbench.c,v 1.13 2007/12/11 00:44:31 sybreon Exp $
  * 
  * AEMB Function Verification C Testbench
  * Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <address@hidden>
@@ -25,6 +25,9 @@
  * 
  * HISTORY
  * $Log: aeMB_testbench.c,v $
+ * Revision 1.13  2007/12/11 00:44:31  sybreon
+ * Modified for AEMB2
+ *
  * Revision 1.12  2007/11/18 19:41:45  sybreon
  * Minor simulation fixes.
  *
@@ -64,6 +67,8 @@
  *
  */
 
+#include "libaemb.h"
+
 /**
    INTERRUPT TEST
 
@@ -72,29 +77,9 @@
    - Interrupt handling
  */
 
-void int_handler (void) __attribute__ ((interrupt_handler));
+void __attribute__ ((interrupt_handler)) int_handler();
 volatile int service = 0xDEADDEAD;
 
-void int_enable()
-{
-  int tmp;  
-  asm volatile ("mfs %0, rmsr;" 
-               "ori %1, %0, 0x02;"
-               "mts rmsr, %1;"
-               : "=r" (tmp)
-               : "r" (tmp));  
-}
-
-void int_disable()
-{
-  int tmp;  
-  asm volatile ("mfs %0, rmsr;" 
-               "andi %1, %0, 0xFD;"
-               "mts rmsr, %1;"
-               : "=r" (tmp)
-               : "r" (tmp));  
-}
-
 void int_service() 
 {
   int* pio = (int*)0xFFFFFFFC;
@@ -329,7 +314,6 @@
    MPI port that is checked by the testbench.
  */
 
-
 int main () 
 {
   // Message Passing Port
@@ -339,13 +323,13 @@
   int max = 10;
 
   // Enable Global Interrupts
-  int_enable();
+  aemb_enable_interrupt();
 
   // INT TEST
-  if (int_test() == -1) { *mpi = 0x4641494C; }
+  //if (int_test() == -1) { *mpi = 0x4641494C; }
 
   // FSL TEST
-  if (fsl_test() == -1) { *mpi = 0x4641494C; }
+  //if (fsl_test() == -1) { *mpi = 0x4641494C; }
 
   // Fibonacci Test
   if (fib_test(max) == -1) { *mpi = 0x4641494C; }
@@ -357,7 +341,8 @@
   if (newton_test(max) == -1) { *mpi = 0x4641494C; }
   
   // Disable Global Interrupts
-  int_disable();
+  aemb_disable_interrupt();
+
   // ALL PASSED
   return 0;
 }

Added: usrp2/trunk/fpga/opencores/aemb/sw/c/libaemb.h
===================================================================
--- usrp2/trunk/fpga/opencores/aemb/sw/c/libaemb.h                              
(rev 0)
+++ usrp2/trunk/fpga/opencores/aemb/sw/c/libaemb.h      2007-12-12 03:24:26 UTC 
(rev 7112)
@@ -0,0 +1,160 @@
+/* $Id: libaemb.h,v 1.1 2007/12/11 00:44:04 sybreon Exp $
+**
+** AEMB2 CUSTOM LIBRARY
+** 
+** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <address@hidden>
+**  
+** This file is part of AEMB.
+**
+** AEMB is free software: you can redistribute it and/or modify it
+** under the terms of the GNU Lesser General Public License as
+** published by the Free Software Foundation, either version 3 of the
+** License, or (at your option) any later version.
+**
+** AEMB is distributed in the hope that it will be useful, but WITHOUT
+** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+** or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
+** Public License for more details.
+**
+** You should have received a copy of the GNU Lesser General Public
+** License along with AEMB. If not, see <http:**www.gnu.org/licenses/>.
+*/
+
+#ifndef LIBAEMB_H
+#define LIBAEMB_H
+
+#define AEMB_TXE 0x10000000
+#define AEMB_TX0 0x20000000
+#define AEMB_TX1 0x40000000
+#define AEMB_BIP 0x00000008
+
+void aemb_reboot () asm ("_program_init");
+inline void aemb_enable_interrupt ();
+inline void aemb_disable_interrupt ();
+inline int aemb_isthread1();
+inline int aemb_isthread0();
+
+/*!
+* Assembly macro to enable MSR_IE
+*/
+void aemb_enable_interrupt ()
+{
+  int msr, tmp;
+  asm volatile ("mfs %0, rmsr;"
+               "ori %1, %0, 0x02;"
+               "mts rmsr, %1;"
+               : "=r"(msr)
+               : "r" (tmp)
+               );
+}
+
+/*!
+* Assembly macro to disable MSR_IE
+*/
+void aemb_disable_interrupt ()
+{
+  int msr, tmp;
+  asm volatile ("mfs %0, rmsr;"
+               "andi %1, %0, 0xFD;"
+               "mts rmsr, %1;"
+               : "=r"(msr)
+               : "r" (tmp)
+               );
+}
+
+/*!
+* Bootstrap Hook Override
+
+* It re-sizes the stack, allocates half to each thread and reboots.
+*/
+
+void aemb_reboot ()
+{
+  asm volatile (// Checks for TXE & BIP flags
+               "mfs     r4, rmsr;"
+               "andi    r3, r4, 0x10000008;"
+               "andi    r6, r4, 0x40000000;"
+               "xori    r18, r3, 0x10000000;"
+               "beqi    r18, 20;"
+               "andi    r4, r4, -9;"
+               "mts     rmsr, r4;"
+
+               // Returns when TXE=0 || BIP=1
+               "rtsd    r15, 8;"
+               "nop;"
+
+               // Calculate new stack
+               "addik   r3, r0, _STACK_SIZE;"  
+               "addik   r5, r0, _stack;"
+               "beqid   r6, 12;"        
+               "sra     r3, r3;"
+               "rsubk   r5, r3, r5;"
+               "addik   r5, r5, -16;"
+
+               // Re-allocate stack
+               "or      r1, r0, r5;"
+               "ori     r4, r4, 8;"
+               "mts     rmsr, r4;"
+
+               // Reboot
+               "brlid   r15, _crtinit;" 
+               "nop;"
+               "brai    exit;" 
+               );  
+}
+
+/*
+void aemb_reboot () 
+{ 
+  int stk_end, stk_siz;
+  int msr, tmp;
+  
+  asm volatile ("mfs %0, rmsr;":"=r"(msr));
+ 
+  if ((msr & AEMB_BIP) || !(msr & AEMB_TXE)) 
+    {
+      msr &= ~AEMB_BIP;
+      asm volatile ("mts rmsr, %0;"::"r"(msr));
+    }
+  else
+    {
+      asm ("la %0, r0, _stack;" : "=r"(stk_end));
+      asm ("la %0, r0, _STACK_SIZE;" : "=r"(stk_siz));
+
+      if (msr & AEMB_TX1) stk_end -= (stk_siz >> 1);     
+
+      stk_end -= 16;     
+
+      asm ("or r1, r0, %0;" :: "r"(stk_end));
+
+      msr |= AEMB_BIP;
+      asm volatile ("mts rmsr, %0;"::"r"(msr));
+
+      asm ("brlid r15, _crtinit;"
+          "nop;"
+          "brai exit;"
+          );
+    }    
+}
+*/
+
+int aemb_isthread1 ()
+{
+  int msr;
+  asm volatile ("mfs %0, rmsr;":"=r"(msr));
+  return (msr & AEMB_TX1);  
+}
+
+int aemb_isthread0 ()
+{
+  int msr;
+  asm volatile ("mfs %0, rmsr;":"=r"(msr));
+  return (msr & AEMB_TX0);  
+}
+
+#endif
+
+/* $Log: libaemb.h,v $
+/* Revision 1.1  2007/12/11 00:44:04  sybreon
+/* initial import
+/* */

Modified: usrp2/trunk/fpga/opencores/aemb/sw/gccrom
===================================================================
--- usrp2/trunk/fpga/opencores/aemb/sw/gccrom   2007-12-11 23:45:06 UTC (rev 
7111)
+++ usrp2/trunk/fpga/opencores/aemb/sw/gccrom   2007-12-12 03:24:26 UTC (rev 
7112)
@@ -1,6 +1,12 @@
 #!/bin/sh
-# $Id: gccrom,v 1.10 2007/11/20 18:35:34 sybreon Exp $
+# $Id: gccrom,v 1.12 2007/12/11 00:44:32 sybreon Exp $
 # $Log: gccrom,v $
+# Revision 1.12  2007/12/11 00:44:32  sybreon
+# Modified for AEMB2
+#
+# Revision 1.11  2007/11/30 17:09:27  sybreon
+# Minor code cleanup.
+#
 # Revision 1.10  2007/11/20 18:35:34  sybreon
 # Generate VMEM instead of HEX dumps of programme.
 #
@@ -35,7 +41,7 @@
 #
 
 # Compile using C++ pre-processor
-mb-g++ -g -mstats -mxl-soft-div -msoft-float -mno-memcpy -msmall-divides -o 
rom.elf $@ && \
+mb-g++ -g  -Wl,-defsym -Wl,_STACK_SIZE=0x400 -mxl-soft-div -msoft-float 
-mxl-barrel-shift -mno-xl-soft-mul -o rom.elf $@ && \
 
 # Create a text listing of the compiled code
 mb-objdump -dSC rom.elf > rom.dump && \
@@ -44,13 +50,8 @@
 mb-objcopy -O srec rom.elf rom.srec && \
 
 # Generate a Verilog VMEM file from the SREC file
-srec_cat rom.srec -o ../sim/dump.rom -vmem 32 && \
+srec_cat rom.srec -o ../sim/dump.vmem -vmem 32 && \
 
-#mb-run -v rom.elf 2> rom.run && \
-#mb-objcopy -O binary rom.elf rom.bin && \
-#hexdump -v -e'1/4 "%.8X\n"' rom.bin > ../sim/aeMB.rom && \
-#rm rom.bin && \
-
 # Cleanup code
 rm rom.srec && \