Re: [Simulavr-devel] irq handling is broken in simulavr

[Joerg Wunsch]

As ThomasK wrote:

> The delay of one opcode comes because of the 2 stage pipline, so the
> OUT instruction to trigger the interrupt will work at the end of
> instruction processing and the next instruction is allways loaded
> and processed before interrupt processing starts? Is it right?

Basically yes.  But it's not a real pipeline.  My guess is that the
output instruction gets in effect by the same rising edge of CPUCLK
which already triggers the next instruction fetch.  Thus, the
interrupt becomes pending when the next instruction is already in the
process of being decoded.

> So, then it's never possible to trigger a interrupt from inside chip 
> without this delay of 1 opcode.

Exactly, that's been Klaus' point.

> Even, if I use SBI instruction instead 
> of OUT instruction.

SBI and OUT do not differ in their timing behaviour.

(AVR Studio "simulator V2")

> Is this code free?

Unfortunately not.  AFAICT, some proprietary software with a very
strict license is used there to translate the Verilog hardware
description into some C code for the simulation.  Similar strict
licensing requirements apply to the generated code, so it is only
allowed to compile it as part of an Atmel product (AVR Studio, or
Atmel Studio).

-- 
cheers, J"org               .-.-.   --... ...--   -.. .  DL8DTL

http://www.sax.de/~joerg/                        NIC: JW11-RIPE
Never trust an operating system you don't have sources for. ;-)