Re: [Simulavr-devel] irq handling is broken in simulavr

[ThomasK]

Hi Jörg,

to see, that I understand it right:

The delay of one opcode comes because of the 2 stage pipline, so the OUT 
instruction to trigger the interrupt will work at the end of instruction 
processing and the next instruction is allways loaded and processed 
before interrupt processing starts? Is it right?

So, then it's never possible to trigger a interrupt from inside chip 
without this delay of 1 opcode. Even, if I use SBI instruction instead 
of OUT instruction.

So, the description in datasheet for the delay on RETI and SEI is right, 
but you have to split between interrupts triggered by code (for example 
enable interrupt flag or trigger interrupt internally by code) and 
interrupts, which have a reason located in environment.

But then it's like to decide between pest and cholera. :-) Anything is 
wrong. Or we have to find a way to "simulate" the pipelining delay for 
writing IO register.

> If anyone is interested, the "Simulator V2" in AVR Studio (for those
> parts where it is supported) is supposed to work exactly the same as
> the hardware, because it uses a model which is directly generated
> after the Verilog code which is used to implement the hardware itself.
> So when in doubt, try it there.

Is this code free? E.g. do we have a possibility to "inspect" this code 
to see, how is it made there?

cu, Thomas