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Re: [Simulavr-devel] Multiple CPU - Architecture discussion


From: Michael Hennebry
Subject: Re: [Simulavr-devel] Multiple CPU - Architecture discussion
Date: Mon, 8 Sep 2008 16:23:22 -0500 (CDT)

Inferred from another post:
swig and avarice are both problems for Windows.
As-is, we could use the trace feature,
but nothing else on Windows.

As header files are for generating code and we want to interpret code,
it would be good if we could use Atmel's XML files, at least indirectly.

We'll need to read data sheets just to figure out how
many different kinds of things, e.g. timers, we need.
If two timers have a different number of associated registers,
we can be fairly certain they are different.
If they have the same number, even if they have the same names,
we'll need to read the data sheet.
Do we want to treat timers as monliths?
Do we want to split them into modes?
Something else?

Do we want to use configuration file to generate
code or to generate CPU instances on the fly?

-- 
Michael   address@hidden
"Pessimist: The glass is half empty.
Optimist:   The glass is half full.
Engineer:   The glass is twice as big as it needs to be."






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