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[PATCH V2 01/14] cris/: fix some comment spelling errors
From: |
zhaolichang |
Subject: |
[PATCH V2 01/14] cris/: fix some comment spelling errors |
Date: |
Fri, 9 Oct 2020 14:44:36 +0800 |
I found that there are many spelling errors in the comments of qemu/target/cris.
I used spellcheck to check the spelling errors and found some errors in the
folder.
Signed-off-by: zhaolichang <zhaolichang@huawei.com>
Reviewed-by: David Edmondson <david.edmondson@oracle.com>
---
target/cris/helper.c | 6 +++---
target/cris/op_helper.c | 2 +-
target/cris/translate.c | 14 +++++++-------
3 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/target/cris/helper.c b/target/cris/helper.c
index b5159b8357..50419e72c5 100644
--- a/target/cris/helper.c
+++ b/target/cris/helper.c
@@ -141,7 +141,7 @@ void crisv10_cpu_do_interrupt(CPUState *cs)
assert(!(env->pregs[PR_CCS] & PFIX_FLAG));
switch (cs->exception_index) {
case EXCP_BREAK:
- /* These exceptions are genereated by the core itself.
+ /* These exceptions are generated by the core itself.
ERP should point to the insn following the brk. */
ex_vec = env->trap_vector;
env->pregs[PRV10_BRP] = env->pc;
@@ -197,7 +197,7 @@ void cris_cpu_do_interrupt(CPUState *cs)
switch (cs->exception_index) {
case EXCP_BREAK:
- /* These exceptions are genereated by the core itself.
+ /* These exceptions are generated by the core itself.
ERP should point to the insn following the brk. */
ex_vec = env->trap_vector;
env->pregs[PR_ERP] = env->pc;
@@ -256,7 +256,7 @@ void cris_cpu_do_interrupt(CPUState *cs)
undefined. */
env->pc = cpu_ldl_code(env, env->pregs[PR_EBP] + ex_vec * 4);
- /* Clear the excption_index to avoid spurios hw_aborts for recursive
+ /* Clear the excption_index to avoid spurious hw_aborts for recursive
bus faults. */
cs->exception_index = -1;
diff --git a/target/cris/op_helper.c b/target/cris/op_helper.c
index 6b1e7ae4a8..3c4aacc26a 100644
--- a/target/cris/op_helper.c
+++ b/target/cris/op_helper.c
@@ -231,7 +231,7 @@ static inline uint32_t
evaluate_flags_writeback(CPUCRISState *env,
{
unsigned int x, z, mask;
- /* Extended arithmetics, leave the z flag alone. */
+ /* Extended arithmetic, leave the z flag alone. */
x = env->cc_x;
mask = env->cc_mask | X_FLAG;
if (x) {
diff --git a/target/cris/translate.c b/target/cris/translate.c
index c312e6f8a6..16b0ef8073 100644
--- a/target/cris/translate.c
+++ b/target/cris/translate.c
@@ -348,7 +348,7 @@ static void t_gen_cris_mstep(TCGv d, TCGv a, TCGv b, TCGv
ccs)
tcg_temp_free(t);
}
-/* Extended arithmetics on CRIS. */
+/* Extended arithmetic on CRIS. */
static inline void t_gen_add_flag(TCGv d, int flag)
{
TCGv c;
@@ -725,7 +725,7 @@ static void cris_alu_op_exec(DisasContext *dc, int op,
switch (op) {
case CC_OP_ADD:
tcg_gen_add_tl(dst, a, b);
- /* Extended arithmetics. */
+ /* Extended arithmetic. */
t_gen_addx_carry(dc, dst);
break;
case CC_OP_ADDC:
@@ -738,7 +738,7 @@ static void cris_alu_op_exec(DisasContext *dc, int op,
break;
case CC_OP_SUB:
tcg_gen_sub_tl(dst, a, b);
- /* Extended arithmetics. */
+ /* Extended arithmetic. */
t_gen_subx_carry(dc, dst);
break;
case CC_OP_MOVE:
@@ -764,7 +764,7 @@ static void cris_alu_op_exec(DisasContext *dc, int op,
break;
case CC_OP_NEG:
tcg_gen_neg_tl(dst, b);
- /* Extended arithmetics. */
+ /* Extended arithmetic. */
t_gen_subx_carry(dc, dst);
break;
case CC_OP_LZ:
@@ -787,7 +787,7 @@ static void cris_alu_op_exec(DisasContext *dc, int op,
break;
case CC_OP_CMP:
tcg_gen_sub_tl(dst, a, b);
- /* Extended arithmetics. */
+ /* Extended arithmetic. */
t_gen_subx_carry(dc, dst);
break;
default:
@@ -3053,12 +3053,12 @@ static unsigned int crisv32_decoder(CPUCRISState *env,
DisasContext *dc)
* On QEMU care needs to be taken when a branch+delayslot sequence is broken
* and the branch and delayslot don't share pages.
*
- * The TB contaning the branch insn will set up env->btarget and evaluate
+ * The TB containing the branch insn will set up env->btarget and evaluate
* env->btaken. When the translation loop exits we will note that the branch
* sequence is broken and let env->dslot be the size of the branch insn (those
* vary in length).
*
- * The TB contaning the delayslot will have the PC of its real insn (i.e no lsb
+ * The TB containing the delayslot will have the PC of its real insn (i.e no
lsb
* set). It will also expect to have env->dslot setup with the size of the
* delay slot so that env->pc - env->dslot point to the branch insn. This TB
* will execute the dslot and take the branch, either to btarget or just one
--
2.26.2.windows.1