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[PULL 10/22] riscv: Pass Object to register_cpu_props instead of DeviceS
From: |
Palmer Dabbelt |
Subject: |
[PULL 10/22] riscv: Pass Object to register_cpu_props instead of DeviceState |
Date: |
Mon, 6 Mar 2023 14:02:47 -0800 |
From: Alexandre Ghiti <alexghiti@rivosinc.com>
One can extract the DeviceState pointer from the Object pointer, so pass
the Object for future commits to access other fields of Object.
No functional changes intended.
Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
Message-ID: <20230303131252.892893-2-alexghiti@rivosinc.com>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
---
target/riscv/cpu.c | 29 +++++++++++++++--------------
1 file changed, 15 insertions(+), 14 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 0ad8f94a42..1c4d8aaa74 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -220,7 +220,7 @@ static const char * const riscv_intr_names[] = {
"reserved"
};
-static void register_cpu_props(DeviceState *dev);
+static void register_cpu_props(Object *obj);
const char *riscv_cpu_get_trap_name(target_ulong cause, bool async)
{
@@ -258,7 +258,7 @@ static void riscv_any_cpu_init(Object *obj)
set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU);
#endif
set_priv_version(env, PRIV_VERSION_1_12_0);
- register_cpu_props(DEVICE(obj));
+ register_cpu_props(obj);
}
#if defined(TARGET_RISCV64)
@@ -267,7 +267,7 @@ static void rv64_base_cpu_init(Object *obj)
CPURISCVState *env = &RISCV_CPU(obj)->env;
/* We set this in the realise function */
set_misa(env, MXL_RV64, 0);
- register_cpu_props(DEVICE(obj));
+ register_cpu_props(obj);
/* Set latest version of privileged specification */
set_priv_version(env, PRIV_VERSION_1_12_0);
}
@@ -276,7 +276,7 @@ static void rv64_sifive_u_cpu_init(Object *obj)
{
CPURISCVState *env = &RISCV_CPU(obj)->env;
set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
- register_cpu_props(DEVICE(obj));
+ register_cpu_props(obj);
set_priv_version(env, PRIV_VERSION_1_10_0);
}
@@ -286,7 +286,7 @@ static void rv64_sifive_e_cpu_init(Object *obj)
RISCVCPU *cpu = RISCV_CPU(obj);
set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU);
- register_cpu_props(DEVICE(obj));
+ register_cpu_props(obj);
set_priv_version(env, PRIV_VERSION_1_10_0);
cpu->cfg.mmu = false;
}
@@ -331,7 +331,7 @@ static void rv128_base_cpu_init(Object *obj)
CPURISCVState *env = &RISCV_CPU(obj)->env;
/* We set this in the realise function */
set_misa(env, MXL_RV128, 0);
- register_cpu_props(DEVICE(obj));
+ register_cpu_props(obj);
/* Set latest version of privileged specification */
set_priv_version(env, PRIV_VERSION_1_12_0);
}
@@ -341,7 +341,7 @@ static void rv32_base_cpu_init(Object *obj)
CPURISCVState *env = &RISCV_CPU(obj)->env;
/* We set this in the realise function */
set_misa(env, MXL_RV32, 0);
- register_cpu_props(DEVICE(obj));
+ register_cpu_props(obj);
/* Set latest version of privileged specification */
set_priv_version(env, PRIV_VERSION_1_12_0);
}
@@ -350,7 +350,7 @@ static void rv32_sifive_u_cpu_init(Object *obj)
{
CPURISCVState *env = &RISCV_CPU(obj)->env;
set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
- register_cpu_props(DEVICE(obj));
+ register_cpu_props(obj);
set_priv_version(env, PRIV_VERSION_1_10_0);
}
@@ -360,7 +360,7 @@ static void rv32_sifive_e_cpu_init(Object *obj)
RISCVCPU *cpu = RISCV_CPU(obj);
set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU);
- register_cpu_props(DEVICE(obj));
+ register_cpu_props(obj);
set_priv_version(env, PRIV_VERSION_1_10_0);
cpu->cfg.mmu = false;
}
@@ -371,7 +371,7 @@ static void rv32_ibex_cpu_init(Object *obj)
RISCVCPU *cpu = RISCV_CPU(obj);
set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU);
- register_cpu_props(DEVICE(obj));
+ register_cpu_props(obj);
set_priv_version(env, PRIV_VERSION_1_11_0);
cpu->cfg.mmu = false;
cpu->cfg.epmp = true;
@@ -383,7 +383,7 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj)
RISCVCPU *cpu = RISCV_CPU(obj);
set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU);
- register_cpu_props(DEVICE(obj));
+ register_cpu_props(obj);
set_priv_version(env, PRIV_VERSION_1_10_0);
cpu->cfg.mmu = false;
}
@@ -398,7 +398,7 @@ static void riscv_host_cpu_init(Object *obj)
#elif defined(TARGET_RISCV64)
set_misa(env, MXL_RV64, 0);
#endif
- register_cpu_props(DEVICE(obj));
+ register_cpu_props(obj);
}
#endif
@@ -1210,11 +1210,12 @@ static Property riscv_cpu_extensions[] = {
* properties and leave. env.misa_ext = 0 means that we want
* all the default properties to be registered.
*/
-static void register_cpu_props(DeviceState *dev)
+static void register_cpu_props(Object *obj)
{
- RISCVCPU *cpu = RISCV_CPU(OBJECT(dev));
+ RISCVCPU *cpu = RISCV_CPU(obj);
uint32_t misa_ext = cpu->env.misa_ext;
Property *prop;
+ DeviceState *dev = DEVICE(obj);
/*
* If misa_ext is not zero, set cfg properties now to
--
2.39.2
- [PULL 00/22] Sixth RISC-V PR for 8.0, Palmer Dabbelt, 2023/03/06
- [PULL 01/22] target/riscv: implement Zicboz extension, Palmer Dabbelt, 2023/03/06
- [PULL 02/22] target/riscv: implement Zicbom extension, Palmer Dabbelt, 2023/03/06
- [PULL 05/22] disas/riscv Fix ctzw disassemble, Palmer Dabbelt, 2023/03/06
- [PULL 03/22] target/riscv: add Zicbop cbo.prefetch{i, r, m} placeholder, Palmer Dabbelt, 2023/03/06
- [PULL 04/22] hw/riscv/virt.c: add cbo[mz]-block-size fdt properties, Palmer Dabbelt, 2023/03/06
- [PULL 06/22] target/riscv: cpu: Implement get_arch_id callback, Palmer Dabbelt, 2023/03/06
- [PULL 08/22] gitlab/opensbi: Move to docker:stable, Palmer Dabbelt, 2023/03/06
- [PULL 07/22] hw: intc: Use cpu_by_arch_id to fetch CPU state, Palmer Dabbelt, 2023/03/06
- [PULL 11/22] riscv: Change type of valid_vm_1_10_[32|64] to bool, Palmer Dabbelt, 2023/03/06
- [PULL 10/22] riscv: Pass Object to register_cpu_props instead of DeviceState,
Palmer Dabbelt <=
- [PULL 12/22] riscv: Allow user to set the satp mode, Palmer Dabbelt, 2023/03/06
- [PULL 14/22] riscv: Correctly set the device-tree entry 'mmu-type', Palmer Dabbelt, 2023/03/06
- [PULL 13/22] riscv: Introduce satp mode hw capabilities, Palmer Dabbelt, 2023/03/06
- [PULL 09/22] roms/opensbi: Upgrade from v1.1 to v1.2, Palmer Dabbelt, 2023/03/06
- [PULL 17/22] hw/riscv/virt: Add memmap pointer to RiscVVirtState, Palmer Dabbelt, 2023/03/06
- [PULL 15/22] hw/riscv/virt: Add OEM_ID and OEM_TABLE_ID fields, Palmer Dabbelt, 2023/03/06
- [PULL 16/22] hw/riscv/virt: Add a switch to disable ACPI, Palmer Dabbelt, 2023/03/06
- [PULL 19/22] hw/riscv/virt: virt-acpi-build.c: Add RINTC in MADT, Palmer Dabbelt, 2023/03/06
- [PULL 18/22] hw/riscv/virt: Enable basic ACPI infrastructure, Palmer Dabbelt, 2023/03/06
- [PULL 22/22] MAINTAINERS: Add entry for RISC-V ACPI, Palmer Dabbelt, 2023/03/06