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[PATCH v2 11/18] target/riscv: gdbstub: Turn on debugger mode before cal
From: |
Bin Meng |
Subject: |
[PATCH v2 11/18] target/riscv: gdbstub: Turn on debugger mode before calling CSR predicate() |
Date: |
Tue, 28 Feb 2023 18:40:27 +0800 |
Since commit 94452ac4cf26 ("target/riscv: remove fflags, frm, and fcsr from
riscv-*-fpu.xml")
the 3 FPU CSRs are removed from the XML target decription. The
original intent of that commit was based on the assumption that
the 3 FPU CSRs will show up in the riscv-csr.xml so the ones in
riscv-*-fpu.xml are redundant. But unforuantely that is not true.
As the FPU CSR predicate() has a run-time check on MSTATUS.FS,
at the time when CSR XML is generated MSTATUS.FS is unset, hence
no FPU CSRs will be reported.
The FPU CSR predicate() already considered such a case of being
accessed by a debugger. All we need to do is to turn on debugger
mode before calling predicate().
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
---
(no changes since v1)
target/riscv/gdbstub.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
index 294f0ceb1c..ef52f41460 100644
--- a/target/riscv/gdbstub.c
+++ b/target/riscv/gdbstub.c
@@ -280,6 +280,10 @@ static int riscv_gen_dynamic_csr_xml(CPUState *cs, int
base_reg)
int bitsize = 16 << env->misa_mxl_max;
int i;
+#if !defined(CONFIG_USER_ONLY)
+ env->debugger = true;
+#endif
+
/* Until gdb knows about 128-bit registers */
if (bitsize > 64) {
bitsize = 64;
@@ -308,6 +312,11 @@ static int riscv_gen_dynamic_csr_xml(CPUState *cs, int
base_reg)
g_string_append_printf(s, "</feature>");
cpu->dyn_csr_xml = g_string_free(s, false);
+
+#if !defined(CONFIG_USER_ONLY)
+ env->debugger = false;
+#endif
+
return CSR_TABLE_SIZE;
}
--
2.25.1
- Re: [PATCH v2 02/18] target/riscv: Add some comments to clarify the priority policy of riscv_csrrw_check(), (continued)
- [PATCH v2 03/18] target/riscv: Use g_assert() for the predicate() NULL check, Bin Meng, 2023/02/28
- [PATCH v2 04/18] target/riscv: gdbstub: Minor change for better readability, Bin Meng, 2023/02/28
- [PATCH v2 05/18] target/riscv: gdbstub: Do not generate CSR XML if Zicsr is disabled, Bin Meng, 2023/02/28
- [PATCH v2 06/18] target/riscv: Coding style fixes in csr.c, Bin Meng, 2023/02/28
- [PATCH v2 07/18] target/riscv: Use 'bool' type for read_only, Bin Meng, 2023/02/28
- [PATCH v2 08/18] target/riscv: Simplify {read, write}_pmpcfg() a little bit, Bin Meng, 2023/02/28
- [PATCH v2 09/18] target/riscv: Simplify getting RISCVCPU pointer from env, Bin Meng, 2023/02/28
- [PATCH v2 10/18] target/riscv: Avoid reporting odd-numbered pmpcfgX in the CSR XML for RV64, Bin Meng, 2023/02/28
- [PATCH v2 11/18] target/riscv: gdbstub: Turn on debugger mode before calling CSR predicate(),
Bin Meng <=
- [PATCH v2 12/18] target/riscv: gdbstub: Drop the vector CSRs in riscv-vector.xml, Bin Meng, 2023/02/28
- [PATCH v2 14/18] target/riscv: Allow debugger to access seed CSR, Bin Meng, 2023/02/28
- [PATCH v2 13/18] target/riscv: Allow debugger to access user timer and counter CSRs, Bin Meng, 2023/02/28
- [PATCH v2 15/18] target/riscv: Allow debugger to access {h, s}stateen CSRs, Bin Meng, 2023/02/28
- [PATCH v2 16/18] target/riscv: Allow debugger to access sstc CSRs, Bin Meng, 2023/02/28
- [PATCH v2 17/18] target/riscv: Drop priv level check in mseccfg predicate(), Bin Meng, 2023/02/28
- [PATCH v2 18/18] target/riscv: Group all predicate() routines together, Bin Meng, 2023/02/28