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[PATCH v2 03/18] target/riscv: Use g_assert() for the predicate() NULL c
From: |
Bin Meng |
Subject: |
[PATCH v2 03/18] target/riscv: Use g_assert() for the predicate() NULL check |
Date: |
Tue, 28 Feb 2023 18:40:19 +0800 |
At present riscv_csrrw_check() checks the CSR predicate() against
NULL and throws RISCV_EXCP_ILLEGAL_INST if it is NULL. But this is
a pure software check, and has nothing to do with the emulation of
the hardware behavior, thus it is inappropriate to return illegal
instruction exception when software forgets to install the hook.
Change to use g_assert() instead.
Signed-off-by: Bin Meng <bmeng@tinylab.org>
---
Changes in v2:
- new patch: Use assert() for the predicate() NULL check
target/riscv/csr.c | 6 +-----
1 file changed, 1 insertion(+), 5 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 4cc2c6370f..cfd7ffc5c2 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -3786,11 +3786,6 @@ static inline RISCVException
riscv_csrrw_check(CPURISCVState *env,
return RISCV_EXCP_ILLEGAL_INST;
}
- /* check predicate */
- if (!csr_ops[csrno].predicate) {
- return RISCV_EXCP_ILLEGAL_INST;
- }
-
/* read / write check */
if (write_mask && read_only) {
return RISCV_EXCP_ILLEGAL_INST;
@@ -3803,6 +3798,7 @@ static inline RISCVException
riscv_csrrw_check(CPURISCVState *env,
* illegal instruction exception should be triggered instead of virtual
* instruction exception. Hence this comes after the read / write check.
*/
+ g_assert(csr_ops[csrno].predicate != NULL);
RISCVException ret = csr_ops[csrno].predicate(env, csrno);
if (ret != RISCV_EXCP_NONE) {
return ret;
--
2.25.1
- [PATCH v2 00/18] target/riscv: Various fixes to gdbstub and CSR access, Bin Meng, 2023/02/28
- [PATCH v2 01/18] target/riscv: gdbstub: Check priv spec version before reporting CSR, Bin Meng, 2023/02/28
- [PATCH v2 02/18] target/riscv: Add some comments to clarify the priority policy of riscv_csrrw_check(), Bin Meng, 2023/02/28
- [PATCH v2 03/18] target/riscv: Use g_assert() for the predicate() NULL check,
Bin Meng <=
- [PATCH v2 04/18] target/riscv: gdbstub: Minor change for better readability, Bin Meng, 2023/02/28
- [PATCH v2 05/18] target/riscv: gdbstub: Do not generate CSR XML if Zicsr is disabled, Bin Meng, 2023/02/28
- [PATCH v2 06/18] target/riscv: Coding style fixes in csr.c, Bin Meng, 2023/02/28
- [PATCH v2 07/18] target/riscv: Use 'bool' type for read_only, Bin Meng, 2023/02/28
- [PATCH v2 08/18] target/riscv: Simplify {read, write}_pmpcfg() a little bit, Bin Meng, 2023/02/28
- [PATCH v2 09/18] target/riscv: Simplify getting RISCVCPU pointer from env, Bin Meng, 2023/02/28
- [PATCH v2 10/18] target/riscv: Avoid reporting odd-numbered pmpcfgX in the CSR XML for RV64, Bin Meng, 2023/02/28
- [PATCH v2 11/18] target/riscv: gdbstub: Turn on debugger mode before calling CSR predicate(), Bin Meng, 2023/02/28
- [PATCH v2 12/18] target/riscv: gdbstub: Drop the vector CSRs in riscv-vector.xml, Bin Meng, 2023/02/28