Re: [PATCH qemu v5 05/14] target/riscv: rvv: Add tail agnostic for vecto

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Re: [PATCH qemu v5 05/14] target/riscv: rvv: Add tail agnostic for vecto

From:	Weiwei Li
Subject:	Re: [PATCH qemu v5 05/14] target/riscv: rvv: Add tail agnostic for vector load / store instructions
Date:	Mon, 28 Mar 2022 19:56:30 +0800
User-agent:	Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.14.0


在 2022/3/7 下午3:10, ~eopxd 写道:

From: eopXD <eop.chen@sifive.com>

Signed-off-by: eop Chen <eop.chen@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
---
  target/riscv/insn_trans/trans_rvv.c.inc |  9 +++++++
  target/riscv/vector_helper.c            | 32 +++++++++++++++++++++++++
  2 files changed, 41 insertions(+)

diff --git a/target/riscv/insn_trans/trans_rvv.c.inc 
b/target/riscv/insn_trans/trans_rvv.c.inc
index cc80bf00ff..66cfc8c603 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -711,6 +711,7 @@ static bool ld_us_op(DisasContext *s, arg_r2nfvm *a, 
uint8_t eew)
      data = FIELD_DP32(data, VDATA, VM, a->vm);
      data = FIELD_DP32(data, VDATA, LMUL, emul);
      data = FIELD_DP32(data, VDATA, NF, a->nf);
+    data = FIELD_DP32(data, VDATA, VTA, s->vta);
      return ldst_us_trans(a->rd, a->rs1, data, fn, s, false);
  }

@@ -748,6 +749,7 @@ static bool st_us_op(DisasContext *s, arg_r2nfvm *a, uint8_t eew)

      data = FIELD_DP32(data, VDATA, VM, a->vm);
      data = FIELD_DP32(data, VDATA, LMUL, emul);
      data = FIELD_DP32(data, VDATA, NF, a->nf);
+    data = FIELD_DP32(data, VDATA, VTA, s->vta);
      return ldst_us_trans(a->rd, a->rs1, data, fn, s, true);
  }

@@ -774,6 +776,7 @@ static bool ld_us_mask_op(DisasContext *s, arg_vlm_v *a, uint8_t eew)

      /* EMUL = 1, NFIELDS = 1 */
      data = FIELD_DP32(data, VDATA, LMUL, 0);
      data = FIELD_DP32(data, VDATA, NF, 1);
+    data = FIELD_DP32(data, VDATA, VTA, s->vta);
      return ldst_us_trans(a->rd, a->rs1, data, fn, s, false);
  }

@@ -791,6 +794,7 @@ static bool st_us_mask_op(DisasContext *s, arg_vsm_v *a, uint8_t eew)

      /* EMUL = 1, NFIELDS = 1 */
      data = FIELD_DP32(data, VDATA, LMUL, 0);
      data = FIELD_DP32(data, VDATA, NF, 1);
+    data = FIELD_DP32(data, VDATA, VTA, s->vta);
      return ldst_us_trans(a->rd, a->rs1, data, fn, s, true);
  }

@@ -862,6 +866,7 @@ static bool ld_stride_op(DisasContext *s, arg_rnfvm *a, uint8_t eew)

      data = FIELD_DP32(data, VDATA, VM, a->vm);
      data = FIELD_DP32(data, VDATA, LMUL, emul);
      data = FIELD_DP32(data, VDATA, NF, a->nf);
+    data = FIELD_DP32(data, VDATA, VTA, s->vta);
      return ldst_stride_trans(a->rd, a->rs1, a->rs2, data, fn, s, false);
  }

@@ -891,6 +896,7 @@ static bool st_stride_op(DisasContext *s, arg_rnfvm *a, uint8_t eew)

      data = FIELD_DP32(data, VDATA, VM, a->vm);
      data = FIELD_DP32(data, VDATA, LMUL, emul);
      data = FIELD_DP32(data, VDATA, NF, a->nf);
+    data = FIELD_DP32(data, VDATA, VTA, s->vta);
      fn = fns[eew];
      if (fn == NULL) {
          return false;
@@ -991,6 +997,7 @@ static bool ld_index_op(DisasContext *s, arg_rnfvm *a, 
uint8_t eew)
      data = FIELD_DP32(data, VDATA, VM, a->vm);
      data = FIELD_DP32(data, VDATA, LMUL, emul);
      data = FIELD_DP32(data, VDATA, NF, a->nf);
+    data = FIELD_DP32(data, VDATA, VTA, s->vta);
      return ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s, false);
  }

@@ -1043,6 +1050,7 @@ static bool st_index_op(DisasContext *s, arg_rnfvm *a, uint8_t eew)

      data = FIELD_DP32(data, VDATA, VM, a->vm);
      data = FIELD_DP32(data, VDATA, LMUL, emul);
      data = FIELD_DP32(data, VDATA, NF, a->nf);
+    data = FIELD_DP32(data, VDATA, VTA, s->vta);
      return ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s, true);
  }

@@ -1108,6 +1116,7 @@ static bool ldff_op(DisasContext *s, arg_r2nfvm *a, uint8_t eew)

      data = FIELD_DP32(data, VDATA, VM, a->vm);
      data = FIELD_DP32(data, VDATA, LMUL, emul);
      data = FIELD_DP32(data, VDATA, NF, a->nf);
+    data = FIELD_DP32(data, VDATA, VTA, s->vta);
      return ldff_trans(a->rd, a->rs1, data, fn, s);
  }

diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c

index 39c79c59c2..1c7015e917 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -289,6 +289,9 @@ vext_ldst_stride(void *vd, void *v0, target_ulong base,
      uint32_t i, k;
      uint32_t nf = vext_nf(desc);
      uint32_t max_elems = vext_max_elems(desc, log2_esz);
+    uint32_t esz = 1 << log2_esz;
+    uint32_t total_elems = vext_get_total_elems(desc, esz);
+    uint32_t vta = vext_vta(desc);

for (i = env->vstart; i < env->vl; i++, env->vstart++) {

          if (!vm && !vext_elem_mask(v0, i)) {
@@ -303,6 +306,11 @@ vext_ldst_stride(void *vd, void *v0, target_ulong base,
          }
      }
      env->vstart = 0;
+    /* set tail elements to 1s */
+    for (k = 0; k < nf; ++k) {
+        vext_set_elems_1s_fns[log2_esz](vd, vta, env->vl + k * total_elems,
+                                        env->vl * esz, total_elems * esz);
+    }
  }

#define GEN_VEXT_LD_STRIDE(NAME, ETYPE, LOAD_FN) \

@@ -348,6 +356,9 @@ vext_ldst_us(void *vd, target_ulong base, CPURISCVState 
*env, uint32_t desc,
      uint32_t i, k;
      uint32_t nf = vext_nf(desc);
      uint32_t max_elems = vext_max_elems(desc, log2_esz);
+    uint32_t esz = 1 << log2_esz;
+    uint32_t total_elems = vext_get_total_elems(desc, esz);
+    uint32_t vta = vext_vta(desc);

/* load bytes from guest memory */

      for (i = env->vstart; i < evl; i++, env->vstart++) {
@@ -359,6 +370,11 @@ vext_ldst_us(void *vd, target_ulong base, CPURISCVState 
*env, uint32_t desc,
          }
      }
      env->vstart = 0;
+    /* set tail elements to 1s */
+    for (k = 0; k < nf; ++k) {
+        vext_set_elems_1s_fns[log2_esz](vd, vta, env->vl + k * total_elems,
+                                        env->vl * esz, total_elems * esz);
+    }
  }


It seems incorrect here. similar to following load/store helper.

In above instructions,  following elements are loaded:

0       *  max_elems          ...     0      *max_elems + vl - 1

1       *  max_elems          ...     1     *max_elems + vl - 1

.......

(nf-1)* max_elems         ...    (nf-1)*max_elems + vl - 1

So, the elements[vl .. max_elems - 1] are tail elements, howeverelements[vl ... 1* total_elems - 1] may not:

elements from max_elems to total_elems - 1 are active elements, Iftotal_elems > max_elems(LMUL< 1)

Or LMUL should be equal or greater than 1 here? I didn't find anydescription about this from the spec.

I also have another question about the tail elements for theseload/store instructions:

when nf = 3, LMUL = 1, vl=vlmax, reg, reg+1, reg+2 will be loaded, thenwhether elements in reg+3


(if they belong to the same register group) are tail elements?

Regards,

Weiwei Li

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[PATCH qemu v5 00/14] Add tail agnostic behavior for rvv instructions, ~eopxd, 2022/03/28
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- [PATCH qemu v5 04/14] target/riscv: rvv: Add tail agnostic for vv instructions, ~eopxd, 2022/03/28
  - Re: [PATCH qemu v5 04/14] target/riscv: rvv: Add tail agnostic for vv instructions, Weiwei Li, 2022/03/28
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- [PATCH qemu v5 05/14] target/riscv: rvv: Add tail agnostic for vector load / store instructions, ~eopxd, 2022/03/28
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    - Re: [PATCH qemu v5 05/14] target/riscv: rvv: Add tail agnostic for vector load / store instructions, eop Chen, 2022/03/30
    - Re: [PATCH qemu v5 05/14] target/riscv: rvv: Add tail agnostic for vector load / store instructions, Weiwei Li, 2022/03/30
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- [PATCH qemu v5 01/14] target/riscv: rvv: Prune redundant ESZ, DSZ parameter passed, ~eopxd, 2022/03/28
- [PATCH qemu v5 10/14] target/riscv: rvv: Add tail agnostic for vector fix-point arithmetic instructions, ~eopxd, 2022/03/28
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