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[PATCH qemu v5 07/14] target/riscv: rvv: Add tail agnostic for vector in
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From: |
~eopxd |
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Subject: |
[PATCH qemu v5 07/14] target/riscv: rvv: Add tail agnostic for vector integer shift instructions |
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Date: |
Mon, 28 Mar 2022 07:20:51 -0000 |
From: eopXD <eop.chen@sifive.com>
Signed-off-by: eop Chen <eop.chen@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn_trans/trans_rvv.c.inc | 11 +++++++++++
target/riscv/vector_helper.c | 12 ++++++++++++
2 files changed, 23 insertions(+)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/insn_trans/trans_rvv.c.inc
index 8dad3fa038..fabb2a78ae 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -1852,6 +1852,16 @@ do_opivx_gvec_shift(DisasContext *s, arg_rmrr *a,
GVecGen2sFn32 *gvec_fn,
}
if (a->vm && s->vl_eq_vlmax) {
+ if (s->vta && s->lmul < 0) {
+ /*
+ * tail elements may pass vlmax when lmul < 0
+ * set tail elements to 1s
+ */
+ uint32_t vlenb = s->cfg_ptr->vlen >> 3;
+ tcg_gen_gvec_ori(s->sew, vreg_ofs(s, a->rd),
+ vreg_ofs(s, a->rd), -1,
+ vlenb, vlenb);
+ }
TCGv_i32 src1 = tcg_temp_new_i32();
tcg_gen_trunc_tl_i32(src1, get_gpr(s, a->rs1, EXT_NONE));
@@ -1910,6 +1920,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)
\
\
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
+ data = FIELD_DP32(data, VDATA, VTA, s->vta); \
tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
vreg_ofs(s, a->rs1), \
vreg_ofs(s, a->rs2), cpu_env, \
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 38ff10fef8..6557a75e79 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -1261,6 +1261,9 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1,
\
{ \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
+ uint32_t esz = sizeof(TS1); \
+ uint32_t total_elems = vext_get_total_elems(desc, esz); \
+ uint32_t vta = vext_vta(desc); \
uint32_t i; \
\
for (i = env->vstart; i < vl; i++) { \
@@ -1272,6 +1275,9 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1,
\
*((TS1 *)vd + HS1(i)) = OP(s2, s1 & MASK); \
} \
env->vstart = 0; \
+ /* set tail elements to 1s */ \
+ vext_set_elems_1s_fns[ctzl(esz)](vd, vta, vl, vl * esz, \
+ total_elems * esz); \
}
GEN_VEXT_SHIFT_VV(vsll_vv_b, uint8_t, uint8_t, H1, H1, DO_SLL, 0x7)
@@ -1296,6 +1302,9 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1,
\
{ \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
+ uint32_t esz = sizeof(TD); \
+ uint32_t total_elems = vext_get_total_elems(desc, esz); \
+ uint32_t vta = vext_vta(desc); \
uint32_t i; \
\
for (i = env->vstart; i < vl; i++) { \
@@ -1306,6 +1315,9 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1,
\
*((TD *)vd + HD(i)) = OP(s2, s1 & MASK); \
} \
env->vstart = 0; \
+ /* set tail elements to 1s */ \
+ vext_set_elems_1s_fns[ctzl(esz)](vd, vta, vl, vl * esz, \
+ total_elems * esz); \
}
GEN_VEXT_SHIFT_VX(vsll_vx_b, uint8_t, int8_t, H1, H1, DO_SLL, 0x7)
--
2.34.1
- [PATCH qemu v5 04/14] target/riscv: rvv: Add tail agnostic for vv instructions, (continued)
- [PATCH qemu v5 04/14] target/riscv: rvv: Add tail agnostic for vv instructions, ~eopxd, 2022/03/28
- [PATCH qemu v5 08/14] target/riscv: rvv: Add tail agnostic for vector integer comparison instructions, ~eopxd, 2022/03/28
- [PATCH qemu v5 06/14] target/riscv: rvv: Add tail agnostic for vx, vvm, vxm instructions, ~eopxd, 2022/03/28
- [PATCH qemu v5 05/14] target/riscv: rvv: Add tail agnostic for vector load / store instructions, ~eopxd, 2022/03/28
[PATCH qemu v5 07/14] target/riscv: rvv: Add tail agnostic for vector integer shift instructions,
~eopxd <=
[PATCH qemu v5 01/14] target/riscv: rvv: Prune redundant ESZ, DSZ parameter passed, ~eopxd, 2022/03/28
[PATCH qemu v5 10/14] target/riscv: rvv: Add tail agnostic for vector fix-point arithmetic instructions, ~eopxd, 2022/03/28
[PATCH qemu v5 12/14] target/riscv: rvv: Add tail agnostic for vector reduction instructions, ~eopxd, 2022/03/28
[PATCH qemu v5 13/14] target/riscv: rvv: Add tail agnostic for vector mask instructions, ~eopxd, 2022/03/28
[PATCH qemu v5 09/14] target/riscv: rvv: Add tail agnostic for vector integer merge and move instructions, ~eopxd, 2022/03/28
[PATCH qemu v5 11/14] target/riscv: rvv: Add tail agnostic for vector floating-point instructions, ~eopxd, 2022/03/28
[PATCH qemu v5 14/14] target/riscv: rvv: Add tail agnostic for vector permutation instructions, ~eopxd, 2022/03/28