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[PATCH v8 06/23] target/riscv: Ignore the pc bits above XLEN
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From: |
LIU Zhiwei |
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Subject: |
[PATCH v8 06/23] target/riscv: Ignore the pc bits above XLEN |
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Date: |
Thu, 20 Jan 2022 20:20:33 +0800 |
The read from PC for translation is in cpu_get_tb_cpu_state, before translation.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 8ebcd57af0..d73925a823 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -43,7 +43,7 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong
*pc,
uint32_t flags = 0;
- *pc = env->pc;
+ *pc = env->xl == MXL_RV32 ? env->pc & UINT32_MAX : env->pc;
*cs_base = 0;
if (riscv_has_ext(env, RVV) || cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f)
{
--
2.25.1
- [PATCH v8 00/23] Support UXL filed in xstatus, LIU Zhiwei, 2022/01/20
- [PATCH v8 01/23] target/riscv: Adjust pmpcfg access with mxl, LIU Zhiwei, 2022/01/20
- [PATCH v8 02/23] target/riscv: Don't save pc when exception return, LIU Zhiwei, 2022/01/20
- [PATCH v8 03/23] target/riscv: Sign extend link reg for jal and jalr, LIU Zhiwei, 2022/01/20
- [PATCH v8 04/23] target/riscv: Sign extend pc for different XLEN, LIU Zhiwei, 2022/01/20
- [PATCH v8 05/23] target/riscv: Create xl field in env, LIU Zhiwei, 2022/01/20
- [PATCH v8 06/23] target/riscv: Ignore the pc bits above XLEN,
LIU Zhiwei <=
- [PATCH v8 07/23] target/riscv: Extend pc for runtime pc write, LIU Zhiwei, 2022/01/20
- [PATCH v8 08/23] target/riscv: Use gdb xml according to max mxlen, LIU Zhiwei, 2022/01/20
- [PATCH v8 09/23] target/riscv: Relax debug check for pm write, LIU Zhiwei, 2022/01/20
- [PATCH v8 10/23] target/riscv: Adjust csr write mask with XLEN, LIU Zhiwei, 2022/01/20
- [PATCH v8 12/23] target/riscv: Alloc tcg global for cur_pm[mask|base], LIU Zhiwei, 2022/01/20
- [PATCH v8 11/23] target/riscv: Create current pm fields in env, LIU Zhiwei, 2022/01/20
- [PATCH v8 13/23] target/riscv: Calculate address according to XLEN, LIU Zhiwei, 2022/01/20
- [PATCH v8 14/23] target/riscv: Split pm_enabled into mask and base, LIU Zhiwei, 2022/01/20
- [PATCH v8 15/23] target/riscv: Split out the vill from vtype, LIU Zhiwei, 2022/01/20
- [PATCH v8 16/23] target/riscv: Adjust vsetvl according to XLEN, LIU Zhiwei, 2022/01/20