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[PATCH v8 02/23] target/riscv: Don't save pc when exception return
From: |
LIU Zhiwei |
Subject: |
[PATCH v8 02/23] target/riscv: Don't save pc when exception return |
Date: |
Thu, 20 Jan 2022 20:20:29 +0800 |
As pc will be written by the xepc in exception return, just ignore
pc in translation.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/helper.h | 4 ++--
target/riscv/insn_trans/trans_privileged.c.inc | 7 ++-----
target/riscv/op_helper.c | 4 ++--
3 files changed, 6 insertions(+), 9 deletions(-)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 6cf6d6ce98..72cc2582f4 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -100,8 +100,8 @@ DEF_HELPER_2(csrr_i128, tl, env, int)
DEF_HELPER_4(csrw_i128, void, env, int, tl, tl)
DEF_HELPER_6(csrrw_i128, tl, env, int, tl, tl, tl, tl)
#ifndef CONFIG_USER_ONLY
-DEF_HELPER_2(sret, tl, env, tl)
-DEF_HELPER_2(mret, tl, env, tl)
+DEF_HELPER_1(sret, tl, env)
+DEF_HELPER_1(mret, tl, env)
DEF_HELPER_1(wfi, void, env)
DEF_HELPER_1(tlb_flush, void, env)
#endif
diff --git a/target/riscv/insn_trans/trans_privileged.c.inc
b/target/riscv/insn_trans/trans_privileged.c.inc
index 75c6ef80a6..6077bbbf11 100644
--- a/target/riscv/insn_trans/trans_privileged.c.inc
+++ b/target/riscv/insn_trans/trans_privileged.c.inc
@@ -74,10 +74,8 @@ static bool trans_uret(DisasContext *ctx, arg_uret *a)
static bool trans_sret(DisasContext *ctx, arg_sret *a)
{
#ifndef CONFIG_USER_ONLY
- tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
-
if (has_ext(ctx, RVS)) {
- gen_helper_sret(cpu_pc, cpu_env, cpu_pc);
+ gen_helper_sret(cpu_pc, cpu_env);
tcg_gen_exit_tb(NULL, 0); /* no chaining */
ctx->base.is_jmp = DISAS_NORETURN;
} else {
@@ -92,8 +90,7 @@ static bool trans_sret(DisasContext *ctx, arg_sret *a)
static bool trans_mret(DisasContext *ctx, arg_mret *a)
{
#ifndef CONFIG_USER_ONLY
- tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
- gen_helper_mret(cpu_pc, cpu_env, cpu_pc);
+ gen_helper_mret(cpu_pc, cpu_env);
tcg_gen_exit_tb(NULL, 0); /* no chaining */
ctx->base.is_jmp = DISAS_NORETURN;
return true;
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index 6f040f2fb9..67693cb42b 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -115,7 +115,7 @@ target_ulong helper_csrrw_i128(CPURISCVState *env, int csr,
#ifndef CONFIG_USER_ONLY
-target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb)
+target_ulong helper_sret(CPURISCVState *env)
{
uint64_t mstatus;
target_ulong prev_priv, prev_virt;
@@ -176,7 +176,7 @@ target_ulong helper_sret(CPURISCVState *env, target_ulong
cpu_pc_deb)
return retpc;
}
-target_ulong helper_mret(CPURISCVState *env, target_ulong cpu_pc_deb)
+target_ulong helper_mret(CPURISCVState *env)
{
if (!(env->priv >= PRV_M)) {
riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
--
2.25.1
- [PATCH v8 00/23] Support UXL filed in xstatus, LIU Zhiwei, 2022/01/20
- [PATCH v8 01/23] target/riscv: Adjust pmpcfg access with mxl, LIU Zhiwei, 2022/01/20
- [PATCH v8 02/23] target/riscv: Don't save pc when exception return,
LIU Zhiwei <=
- [PATCH v8 03/23] target/riscv: Sign extend link reg for jal and jalr, LIU Zhiwei, 2022/01/20
- [PATCH v8 04/23] target/riscv: Sign extend pc for different XLEN, LIU Zhiwei, 2022/01/20
- [PATCH v8 05/23] target/riscv: Create xl field in env, LIU Zhiwei, 2022/01/20
- [PATCH v8 06/23] target/riscv: Ignore the pc bits above XLEN, LIU Zhiwei, 2022/01/20
- [PATCH v8 07/23] target/riscv: Extend pc for runtime pc write, LIU Zhiwei, 2022/01/20
- [PATCH v8 08/23] target/riscv: Use gdb xml according to max mxlen, LIU Zhiwei, 2022/01/20
- [PATCH v8 09/23] target/riscv: Relax debug check for pm write, LIU Zhiwei, 2022/01/20
- [PATCH v8 10/23] target/riscv: Adjust csr write mask with XLEN, LIU Zhiwei, 2022/01/20
- [PATCH v8 12/23] target/riscv: Alloc tcg global for cur_pm[mask|base], LIU Zhiwei, 2022/01/20
- [PATCH v8 11/23] target/riscv: Create current pm fields in env, LIU Zhiwei, 2022/01/20