Re: [PATCH v5 3/5] target/riscv: add support for svnapot extension

[Weiwei Li]

在 2022/1/18 上午11:32, Anup Patel 写道:
> On Tue, Jan 18, 2022 at 6:47 AM Weiwei Li <liweiwei@iscas.ac.cn> wrote:
> > - add PTE_N bit
> > - add PTE_N bit check for inner PTE
> > - update address translation to support 64KiB continuous region (napot_bits = 4)
> >
> > Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
> > Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
> > Cc: Anup Patel <anup@brainfault.org>
> I did review this patch previously.
>
> In any case, this looks good to me.
>
> Reviewed-by: Anup Patel <anup@brainfault.org>
>
> Regards,
> Anup

Thanks a lot. Sorry for your repeated work.

Regards.

Weiwei Li

> > ---
> >   target/riscv/cpu.c        |  2 ++
> >   target/riscv/cpu.h        |  1 +
> >   target/riscv/cpu_bits.h   |  1 +
> >   target/riscv/cpu_helper.c | 18 +++++++++++++++---
> >   4 files changed, 19 insertions(+), 3 deletions(-)
> >
> > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> > index 9bc25d3055..ff6c86c85b 100644
> > --- a/target/riscv/cpu.c
> > +++ b/target/riscv/cpu.c
> > @@ -668,6 +668,8 @@ static Property riscv_cpu_properties[] = {
> >       DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
> >       DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
> >
> > +    DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false),
> > +
> >       DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true),
> >       DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true),
> >       DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true),
> > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> > index 4d63086765..d3d17cde82 100644
> > --- a/target/riscv/cpu.h
> > +++ b/target/riscv/cpu.h
> > @@ -327,6 +327,7 @@ struct RISCVCPU {
> >           bool ext_counters;
> >           bool ext_ifencei;
> >           bool ext_icsr;
> > +        bool ext_svnapot;
> >           bool ext_zfh;
> >           bool ext_zfhmin;
> >
> > diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> > index 282cd8eecd..5501e9698b 100644
> > --- a/target/riscv/cpu_bits.h
> > +++ b/target/riscv/cpu_bits.h
> > @@ -486,6 +486,7 @@ typedef enum {
> >   #define PTE_A               0x040 /* Accessed */
> >   #define PTE_D               0x080 /* Dirty */
> >   #define PTE_SOFT            0x300 /* Reserved for Software */
> > +#define PTE_N               0x8000000000000000 /* NAPOT translation */
> >
> >   /* Page table PPN shift amount */
> >   #define PTE_PPN_SHIFT       10
> > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> > index 1820188f41..c276760c7f 100644
> > --- a/target/riscv/cpu_helper.c
> > +++ b/target/riscv/cpu_helper.c
> > @@ -621,12 +621,13 @@ restart:
> >
> >           hwaddr ppn = (pte & PTE_PPN_MASK) >> PTE_PPN_SHIFT;
> >
> > +        RISCVCPU *cpu = env_archcpu(env);
> >           if (!(pte & PTE_V)) {
> >               /* Invalid PTE */
> >               return TRANSLATE_FAIL;
> >           } else if (!(pte & (PTE_R | PTE_W | PTE_X))) {
> >               /* Inner PTE, continue walking */
> > -            if (pte & (PTE_D | PTE_A | PTE_U)) {
> > +            if (pte & (target_ulong)(PTE_D | PTE_A | PTE_U | PTE_N)) {
> >                   return TRANSLATE_FAIL;
> >               }
> >               base = ppn << PGSHIFT;
> > @@ -702,8 +703,19 @@ restart:
> >               /* for superpage mappings, make a fake leaf PTE for the TLB's
> >                  benefit. */
> >               target_ulong vpn = addr >> PGSHIFT;
> > -            *physical = ((ppn | (vpn & ((1L << ptshift) - 1))) << PGSHIFT) |
> > -                        (addr & ~TARGET_PAGE_MASK);
> > +
> > +            int napot_bits = 0;
> > +            if (cpu->cfg.ext_svnapot && (pte & (target_ulong)PTE_N)) {
> > +                napot_bits = ctzl(ppn) + 1;
> > +                if ((i != (levels - 1)) || (napot_bits != 4)) {
> > +                    return TRANSLATE_FAIL;
> > +                }
> > +            }
> > +
> > +            *physical = (((ppn & ~(((target_ulong)1 << napot_bits) - 1)) |
> > +                          (vpn & (((target_ulong)1 << napot_bits) - 1)) |
> > +                          (vpn & (((target_ulong)1 << ptshift) - 1))
> > +                        ) << PGSHIFT) | (addr & ~TARGET_PAGE_MASK);
> >
> >               /* set permissions on the TLB entry */
> >               if ((pte & PTE_R) || ((pte & PTE_X) && mxr)) {
> > --
> > 2.17.1