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[PATCH v7 12/23] target/riscv: Implement AIA interrupt filtering CSRs
From: |
Anup Patel |
Subject: |
[PATCH v7 12/23] target/riscv: Implement AIA interrupt filtering CSRs |
Date: |
Mon, 17 Jan 2022 18:58:15 +0530 |
From: Anup Patel <anup.patel@wdc.com>
The AIA specificaiton adds interrupt filtering support for M-mode
and HS-mode. Using AIA interrupt filtering M-mode and H-mode can
take local interrupt 13 or above and selectively inject same local
interrupt to lower privilege modes.
At the moment, we don't have any local interrupts above 12 so we
add dummy implementation (i.e. read zero and ignore write) of AIA
interrupt filtering CSRs.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/csr.c | 23 +++++++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index f0d8cb097b..d018cbae72 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -154,6 +154,15 @@ static RISCVException any32(CPURISCVState *env, int csrno)
}
+static int aia_any(CPURISCVState *env, int csrno)
+{
+ if (!riscv_feature(env, RISCV_FEATURE_AIA)) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+
+ return any(env, csrno);
+}
+
static int aia_any32(CPURISCVState *env, int csrno)
{
if (!riscv_feature(env, RISCV_FEATURE_AIA)) {
@@ -553,6 +562,12 @@ static RISCVException read_zero(CPURISCVState *env, int
csrno,
return RISCV_EXCP_NONE;
}
+static RISCVException write_ignore(CPURISCVState *env, int csrno,
+ target_ulong val)
+{
+ return RISCV_EXCP_NONE;
+}
+
static RISCVException read_mhartid(CPURISCVState *env, int csrno,
target_ulong *val)
{
@@ -2524,9 +2539,15 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
[CSR_MTVAL] = { "mtval", any, read_mtval, write_mtval },
[CSR_MIP] = { "mip", any, NULL, NULL, rmw_mip },
+ /* Virtual Interrupts for Supervisor Level (AIA) */
+ [CSR_MVIEN] = { "mvien", aia_any, read_zero, write_ignore },
+ [CSR_MVIP] = { "mvip", aia_any, read_zero, write_ignore },
+
/* Machine-Level High-Half CSRs (AIA) */
[CSR_MIDELEGH] = { "midelegh", aia_any32, NULL, NULL, rmw_midelegh },
[CSR_MIEH] = { "mieh", aia_any32, NULL, NULL, rmw_mieh },
+ [CSR_MVIENH] = { "mvienh", aia_any32, read_zero, write_ignore },
+ [CSR_MVIPH] = { "mviph", aia_any32, read_zero, write_ignore },
[CSR_MIPH] = { "miph", aia_any32, NULL, NULL, rmw_miph },
/* Supervisor Trap Setup */
@@ -2580,12 +2601,14 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
[CSR_MTINST] = { "mtinst", hmode, read_mtinst,
write_mtinst },
/* Virtual Interrupts and Interrupt Priorities (H-extension with AIA) */
+ [CSR_HVIEN] = { "hvien", aia_hmode, read_zero, write_ignore },
[CSR_HVICTL] = { "hvictl", aia_hmode, read_hvictl, write_hvictl
},
[CSR_HVIPRIO1] = { "hviprio1", aia_hmode, read_hviprio1,
write_hviprio1 },
[CSR_HVIPRIO2] = { "hviprio2", aia_hmode, read_hviprio2,
write_hviprio2 },
/* Hypervisor and VS-Level High-Half CSRs (H-extension with AIA) */
[CSR_HIDELEGH] = { "hidelegh", aia_hmode32, NULL, NULL, rmw_hidelegh
},
+ [CSR_HVIENH] = { "hvienh", aia_hmode32, read_zero, write_ignore
},
[CSR_HVIPH] = { "hviph", aia_hmode32, NULL, NULL, rmw_hviph },
[CSR_HVIPRIO1H] = { "hviprio1h", aia_hmode32, read_hviprio1h,
write_hviprio1h },
[CSR_HVIPRIO2H] = { "hviprio2h", aia_hmode32, read_hviprio2h,
write_hviprio2h },
--
2.25.1
- [PATCH v7 00/23] QEMU RISC-V AIA support, Anup Patel, 2022/01/17
- [PATCH v7 03/23] target/riscv: Implement hgeie and hgeip CSRs, Anup Patel, 2022/01/17
- [PATCH v7 02/23] target/riscv: Implement SGEIP bit in hip and hie CSRs, Anup Patel, 2022/01/17
- [PATCH v7 04/23] target/riscv: Improve delivery of guest external interrupts, Anup Patel, 2022/01/17
- [PATCH v7 14/23] target/riscv: Implement AIA xiselect and xireg CSRs, Anup Patel, 2022/01/17
- [PATCH v7 12/23] target/riscv: Implement AIA interrupt filtering CSRs,
Anup Patel <=
- [PATCH v7 13/23] target/riscv: Implement AIA mtopi, stopi, and vstopi CSRs, Anup Patel, 2022/01/17
- [PATCH v7 11/23] target/riscv: Implement AIA hvictl and hviprioX CSRs, Anup Patel, 2022/01/17
- [PATCH v7 10/23] target/riscv: Implement AIA CSRs for 64 local interrupts on RV32, Anup Patel, 2022/01/17
- [PATCH v7 15/23] target/riscv: Implement AIA IMSIC interface CSRs, Anup Patel, 2022/01/17
- [PATCH v7 09/23] target/riscv: Implement AIA local interrupt priorities, Anup Patel, 2022/01/17
- [PATCH v7 16/23] hw/riscv: virt: Use AIA INTC compatible string when available, Anup Patel, 2022/01/17