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[PATCH v6 17/22] target/riscv: Remove VILL field in VTYPE
From: |
LIU Zhiwei |
Subject: |
[PATCH v6 17/22] target/riscv: Remove VILL field in VTYPE |
Date: |
Thu, 13 Jan 2022 19:39:59 +0800 |
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Acked-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 645a1b3f6c..85eb5c63cf 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -110,7 +110,6 @@ FIELD(VTYPE, VTA, 6, 1)
FIELD(VTYPE, VMA, 7, 1)
FIELD(VTYPE, VEDIV, 8, 2)
FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - 11)
-FIELD(VTYPE, VILL, sizeof(target_ulong) * 8 - 1, 1)
struct CPURISCVState {
target_ulong gpr[32];
--
2.25.1
- [PATCH v6 07/22] target/riscv: Extend pc for runtime pc write, (continued)
- [PATCH v6 07/22] target/riscv: Extend pc for runtime pc write, LIU Zhiwei, 2022/01/13
- [PATCH v6 08/22] target/riscv: Use gdb xml according to max mxlen, LIU Zhiwei, 2022/01/13
- [PATCH v6 09/22] target/riscv: Relax debug check for pm write, LIU Zhiwei, 2022/01/13
- [PATCH v6 10/22] target/riscv: Adjust csr write mask with XLEN, LIU Zhiwei, 2022/01/13
- [PATCH v6 11/22] target/riscv: Create current pm fields in env, LIU Zhiwei, 2022/01/13
- [PATCH v6 12/22] target/riscv: Alloc tcg global for cur_pm[mask|base], LIU Zhiwei, 2022/01/13
- [PATCH v6 13/22] target/riscv: Calculate address according to XLEN, LIU Zhiwei, 2022/01/13
- [PATCH v6 14/22] target/riscv: Split pm_enabled into mask and base, LIU Zhiwei, 2022/01/13
- [PATCH v6 15/22] target/riscv: Split out the vill from vtype, LIU Zhiwei, 2022/01/13
- [PATCH v6 16/22] target/riscv: Adjust vsetvl according to XLEN, LIU Zhiwei, 2022/01/13
- [PATCH v6 17/22] target/riscv: Remove VILL field in VTYPE,
LIU Zhiwei <=
- [PATCH v6 18/22] target/riscv: Fix check range for first fault only, LIU Zhiwei, 2022/01/13
- [PATCH v6 19/22] target/riscv: Adjust vector address with mask, LIU Zhiwei, 2022/01/13
- [PATCH v6 20/22] target/riscv: Adjust scalar reg in vector with XLEN, LIU Zhiwei, 2022/01/13
- [PATCH v6 21/22] target/riscv: Enable uxl field write, LIU Zhiwei, 2022/01/13
- [PATCH v6 22/22] target/riscv: Relax UXL field for debugging, LIU Zhiwei, 2022/01/13