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[PATCH v6 20/22] target/riscv: Adjust scalar reg in vector with XLEN
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From: |
LIU Zhiwei |
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Subject: |
[PATCH v6 20/22] target/riscv: Adjust scalar reg in vector with XLEN |
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Date: |
Thu, 13 Jan 2022 19:40:02 +0800 |
When sew <= 32bits, not need to extend scalar reg.
When sew > 32bits, if xlen is less that sew, we should sign extend
the scalar register, except explicitly specified by the spec.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
target/riscv/insn_trans/trans_rvv.c.inc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/insn_trans/trans_rvv.c.inc
index 1c8086d3a6..b6502cdc7c 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -1201,7 +1201,7 @@ static bool opivx_trans(uint32_t vd, uint32_t rs1,
uint32_t vs2, uint32_t vm,
dest = tcg_temp_new_ptr();
mask = tcg_temp_new_ptr();
src2 = tcg_temp_new_ptr();
- src1 = get_gpr(s, rs1, EXT_NONE);
+ src1 = get_gpr(s, rs1, EXT_SIGN);
data = FIELD_DP32(data, VDATA, VM, vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
--
2.25.1
- [PATCH v6 10/22] target/riscv: Adjust csr write mask with XLEN, (continued)
- [PATCH v6 10/22] target/riscv: Adjust csr write mask with XLEN, LIU Zhiwei, 2022/01/13
- [PATCH v6 11/22] target/riscv: Create current pm fields in env, LIU Zhiwei, 2022/01/13
- [PATCH v6 12/22] target/riscv: Alloc tcg global for cur_pm[mask|base], LIU Zhiwei, 2022/01/13
- [PATCH v6 13/22] target/riscv: Calculate address according to XLEN, LIU Zhiwei, 2022/01/13
- [PATCH v6 14/22] target/riscv: Split pm_enabled into mask and base, LIU Zhiwei, 2022/01/13
- [PATCH v6 15/22] target/riscv: Split out the vill from vtype, LIU Zhiwei, 2022/01/13
- [PATCH v6 16/22] target/riscv: Adjust vsetvl according to XLEN, LIU Zhiwei, 2022/01/13
- [PATCH v6 17/22] target/riscv: Remove VILL field in VTYPE, LIU Zhiwei, 2022/01/13
- [PATCH v6 18/22] target/riscv: Fix check range for first fault only, LIU Zhiwei, 2022/01/13
- [PATCH v6 19/22] target/riscv: Adjust vector address with mask, LIU Zhiwei, 2022/01/13
- [PATCH v6 20/22] target/riscv: Adjust scalar reg in vector with XLEN,
LIU Zhiwei <=
- [PATCH v6 21/22] target/riscv: Enable uxl field write, LIU Zhiwei, 2022/01/13
- [PATCH v6 22/22] target/riscv: Relax UXL field for debugging, LIU Zhiwei, 2022/01/13