Re: [PATCH v8 07/18] target/riscv: setup everything for rv64 to support rv128 execution

[Alistair Francis]

On Fri, Jan 7, 2022 at 4:23 PM Frédéric Pétrot
<frederic.petrot@univ-grenoble-alpes.fr> wrote:
>
> On 06/01/2022 22:24, Alistair Francis wrote:
> > On Fri, Jan 7, 2022 at 7:04 AM Frédéric Pétrot
> > <frederic.petrot@univ-grenoble-alpes.fr> wrote:
> >>
> >> This patch adds the support of the '-cpu rv128' option to
> >> qemu-system-riscv64 so that we can indicate that we want to run rv128
> >> executables.
> >> Still, there is no support for 128-bit insns at that stage so qemu fails
> >> miserably (as expected) if launched with this option.
> >>
> >> Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
> >> Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
> >> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
> >> ---
> >>   include/disas/dis-asm.h |  1 +
> >>   target/riscv/cpu.h      |  1 +
> >>   disas/riscv.c           |  5 +++++
> >>   target/riscv/cpu.c      | 20 ++++++++++++++++++++
> >>   target/riscv/gdbstub.c  |  5 +++++
> >>   5 files changed, 32 insertions(+)
> >>
> >> diff --git a/include/disas/dis-asm.h b/include/disas/dis-asm.h
> >> index 08e1beec85..102a1e7f50 100644
> >> --- a/include/disas/dis-asm.h
> >> +++ b/include/disas/dis-asm.h
> >> @@ -459,6 +459,7 @@ int print_insn_nios2(bfd_vma, disassemble_info*);
> >>   int print_insn_xtensa           (bfd_vma, disassemble_info*);
> >>   int print_insn_riscv32          (bfd_vma, disassemble_info*);
> >>   int print_insn_riscv64          (bfd_vma, disassemble_info*);
> >> +int print_insn_riscv128         (bfd_vma, disassemble_info*);
> >>   int print_insn_rx(bfd_vma, disassemble_info *);
> >>   int print_insn_hexagon(bfd_vma, disassemble_info *);
> >>
> >> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> >> index fa5d238530..efe481f5fb 100644
> >> --- a/target/riscv/cpu.h
> >> +++ b/target/riscv/cpu.h
> >> @@ -38,6 +38,7 @@
> >>   #define TYPE_RISCV_CPU_ANY              RISCV_CPU_TYPE_NAME("any")
> >>   #define TYPE_RISCV_CPU_BASE32           RISCV_CPU_TYPE_NAME("rv32")
> >>   #define TYPE_RISCV_CPU_BASE64           RISCV_CPU_TYPE_NAME("rv64")
> >> +#define TYPE_RISCV_CPU_BASE128          RISCV_CPU_TYPE_NAME("rv128")
> >
> > As this series only adds partial support for 128-bit support, I think
> > we should probably change this to "x-rv128". That way we indicate to
> > users that it is experimental. That allows us more flexibility in the
> > future to have breaking changes and will hopefully avoid confusion
> > about the current state. What do you think? I can just make the change
> > when I apply the patches.
>
>    Sure, this is clearly experimental (the spec is a draft) and should be
>    marked so, I totally agree. Please make the change as you suggest,

Great!

Applied to riscv-to-apply.next

If you want to make sure my change didn't break anything you can test
the tree here: https://github.com/alistair23/qemu/tree/riscv-to-apply.next

I'll send a PR this weekend or next week.

Alistair

>
>    Thanks,
>    Frédéric
>
> >
> > Alistair
>
> --
> +---------------------------------------------------------------------------+
> | Frédéric Pétrot, Pr. Grenoble INP-Ensimag/TIMA,   Ensimag deputy director |
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> | http://tima.univ-grenoble-alpes.fr frederic.petrot@univ-grenoble-alpes.fr |
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