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Re: [PATCH v4 02/11] target/riscv: Implement PMU CSR predicate function
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From: |
Bin Meng |
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Subject: |
Re: [PATCH v4 02/11] target/riscv: Implement PMU CSR predicate function for S-mode |
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Date: |
Fri, 7 Jan 2022 15:50:53 +0800 |
On Fri, Jan 7, 2022 at 10:14 AM Atish Patra <atishp@rivosinc.com> wrote:
>
> From: Atish Patra <atish.patra@wdc.com>
>
> Currently, the predicate function for PMU related CSRs only works if
> virtualization is enabled. It also does not check mcounteren bits before
> before cycle/minstret/hpmcounterx access.
>
> Support supervisor mode access in the predicate function as well.
>
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
> Signed-off-by: Atish Patra <atish.patra@wdc.com>
> Signed-off-by: Atish Patra <atishp@rivosinc.com>
> ---
> target/riscv/csr.c | 52 ++++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 52 insertions(+)
>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
- [PATCH v4 03/11] target/riscv: pmu: Rename the counters extension to pmu, (continued)
- [PATCH v4 01/11] target/riscv: Fix PMU CSR predicate function, Atish Patra, 2022/01/06
- [PATCH v4 08/11] target/riscv: Add sscofpmf extension support, Atish Patra, 2022/01/06
- [PATCH v4 02/11] target/riscv: Implement PMU CSR predicate function for S-mode, Atish Patra, 2022/01/06
- Re: [PATCH v4 02/11] target/riscv: Implement PMU CSR predicate function for S-mode,
Bin Meng <=
- [PATCH v4 04/11] target/riscv: pmu: Make number of counters configurable, Atish Patra, 2022/01/06
- [PATCH v4 09/11] target/riscv: Simplify counter predicate function, Atish Patra, 2022/01/06