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[PATCH v4 10/17] target/riscv: support for 128-bit U-type instructions
From: |
Frédéric Pétrot |
Subject: |
[PATCH v4 10/17] target/riscv: support for 128-bit U-type instructions |
Date: |
Mon, 25 Oct 2021 14:28:11 +0200 |
Adding the 128-bit version of lui and auipc, and introducing to that end
a set register with immediat function to handle extension on 128 bits.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
---
target/riscv/translate.c | 22 ++++++++++++++++++++++
target/riscv/insn_trans/trans_rvi.c.inc | 8 ++++----
2 files changed, 26 insertions(+), 4 deletions(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index b183ad2b6e..ab706d799a 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -282,6 +282,28 @@ static void gen_set_gpr(DisasContext *ctx, int reg_num,
TCGv t)
}
}
+static void gen_set_gpri(DisasContext *ctx, int reg_num, target_long imm)
+{
+ if (reg_num != 0) {
+ switch (get_ol(ctx)) {
+ case MXL_RV32:
+ tcg_gen_movi_tl(cpu_gpr[reg_num], imm);
+ tcg_gen_ext32s_tl(cpu_gpr[reg_num], cpu_gpr[reg_num]);
+ break;
+ case MXL_RV64:
+ case MXL_RV128:
+ tcg_gen_movi_tl(cpu_gpr[reg_num], imm);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+
+ if (get_xl_max(ctx) == MXL_RV128) {
+ tcg_gen_movi_tl(cpu_gprh[reg_num], -(imm < 0));
+ }
+ }
+}
+
static void gen_set_gpr128(DisasContext *ctx, int reg_num, TCGv rl, TCGv rh)
{
if (get_ol(ctx) != MXL_RV128) {
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc
b/target/riscv/insn_trans/trans_rvi.c.inc
index d17bde6a3a..3222a45d72 100644
--- a/target/riscv/insn_trans/trans_rvi.c.inc
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -26,14 +26,14 @@ static bool trans_illegal(DisasContext *ctx, arg_empty *a)
static bool trans_c64_illegal(DisasContext *ctx, arg_empty *a)
{
- REQUIRE_64BIT(ctx);
- return trans_illegal(ctx, a);
+ REQUIRE_64_OR_128BIT(ctx);
+ return trans_illegal(ctx, a);
}
static bool trans_lui(DisasContext *ctx, arg_lui *a)
{
if (a->rd != 0) {
- tcg_gen_movi_tl(cpu_gpr[a->rd], a->imm);
+ gen_set_gpri(ctx, a->rd, a->imm);
}
return true;
}
@@ -41,7 +41,7 @@ static bool trans_lui(DisasContext *ctx, arg_lui *a)
static bool trans_auipc(DisasContext *ctx, arg_auipc *a)
{
if (a->rd != 0) {
- tcg_gen_movi_tl(cpu_gpr[a->rd], a->imm + ctx->base.pc_next);
+ gen_set_gpri(ctx, a->rd, a->imm + ctx->base.pc_next);
}
return true;
}
--
2.33.0
- Re: [PATCH v4 04/17] target/riscv: separation of bitwise logic and aritmetic helpers, (continued)
- [PATCH v4 09/17] target/riscv: support for 128-bit bitwise instructions, Frédéric Pétrot, 2021/10/25
- [PATCH v4 08/17] target/riscv: accessors to registers upper part and 128-bit load/store, Frédéric Pétrot, 2021/10/25
- [PATCH v4 06/17] target/riscv: setup everything so that riscv128-softmmu compiles, Frédéric Pétrot, 2021/10/25
- [PATCH v4 07/17] target/riscv: moving some insns close to similar insns, Frédéric Pétrot, 2021/10/25
- [PATCH v4 10/17] target/riscv: support for 128-bit U-type instructions,
Frédéric Pétrot <=
- [PATCH v4 11/17] target/riscv: support for 128-bit shift instructions, Frédéric Pétrot, 2021/10/25
- [PATCH v4 13/17] target/riscv: support for 128-bit M extension, Frédéric Pétrot, 2021/10/25
- [PATCH v4 14/17] target/riscv: adding high part of some csrs, Frédéric Pétrot, 2021/10/25
- [PATCH v4 16/17] target/riscv: modification of the trans_csrxx for 128-bit support, Frédéric Pétrot, 2021/10/25
- [PATCH v4 15/17] target/riscv: helper functions to wrap calls to 128-bit csr insns, Frédéric Pétrot, 2021/10/25
- [PATCH v4 17/17] target/riscv: actual functions to realize crs 128-bit insns, Frédéric Pétrot, 2021/10/25
- [PATCH v4 12/17] target/riscv: support for 128-bit arithmetic instructions, Frédéric Pétrot, 2021/10/25